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Ring-VCO-based phase-locked loops for clock generation–design considerations and state-of-the-art
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作者 Shiheng Yang Jun Yin +7 位作者 yueduo liu Zihao Zhu Rongxin Bao Jiahui Lin Haoran Li Qiang Li Pui-In Mak Rui P.Martins 《Chip》 2023年第2期34-43,共10页
This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objec... This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power,jitter and area.An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analyt-ically and benchmarked with respect to their figure-of-merit(FoM).The paper also summarizes the key concerns on the selection of dif-ferent circuit techniques to optimize the clock performance under dif-ferent scenarios. 展开更多
关键词 Clock generation IC design Phase-locked loop(PLL) Frequency synthesizer
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