Compressed SNR-and-Channel Estimation for Beam Tracking in 60-GHz WLAN

Signal-to-noise ratio （SNR） and channel estimations are critical for 60-GHz communications to track the optimal trans- mission and reception beam pairs. However, the excessive pilot overhead for the estima- tions severely reduces system throughput in fast-rotation scenarios. In order to address this problem, we firstly demonstrate the potential sparseness property of 60-GHz channel in beam tracking; subsequently, via exploiting this property, we propose a novel compressed SNR-and-channel estimation. The estimation is conducted in a three-stage fashion, includ- ing the unstructured estimation, nonzero-tap detection, and structured estimation with non- zero-tap location. Numerical simulations show that, in the case of substantial reduction of the pilot overhead, the proposed estimator still reveals a significant improvement in terms of estimation performance over the scheme in IEEE 802.1 lad. Furthermore, it is also demon- strated that the proposed SNR and channel estimators can approach the lower bounds in sparse channels so long as SNR exceeds 8 dB.

Hardware/software co-verification platform for EOS design

Ethernet over SDH/SONET (EOS) is a hotspot in today's data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However, implementing an EOS system on a chip is complex and needs full verifications. This paper introduces our design of Hardware/Software co-verification platform for EOS design. The hardware platform contains a microprocessor board and an FPGA (Field Programmable Gate Array)-based verification board, and the corresponding software includes test benches running in FPGAs, controlling programs for the microprocessor and a console program with GUI (Graphical User Interface) interface for configuration, management and supervision. The design is cost-effective and has been successfully employed to verify several IP (Intellectual Property) blocks of our EOS chip. Moreover, it is flexible and can be applied as a general-purpose verification platform.

An integrated self-healing algorithm for resilient packet ring

Resilient Packet Ring (RPR) is a Media Access Control (MAC) layer protocol that operates over a double counter-rotating ring network topology. RPR is designed to enhance Synchronous Digital Hierarchy(SDH) in order to handle data traffic more efficiently. Since Intelligent Protection Switching(IPS) is one of the key technologies in ring networks, RPR provides two intelligent protection algorithms: steering and wrapping. While wrapping in RPR in essence inherits the automatic protection switching(APS) algorithm of SDH, it also wastes the bandwidth on the wrapping ringlets and may result in severe congestion. Whereas steering in RPR provides high bandwidth utilization, its switching speed is low, because it is indeed a high layer's restoration algorithm. In this paper, integrated self-healing(ISH) algorithm as an effective algorithm for RPR is proposed, which synthesizes the merits of the two algorithms by transporting healing signal and computing routing in MAC layer. At last, the performance of ISH algorithm is analyzed and simulated.

0.18μm CMOS, MONOLITHIC MSTP ASIC

A highly integrated monolithic Multi-Service Transport Platform （MSTP） Application Specified Integrated Circuit （AS1C） MSEOSX8-6 has been fabricated with 0.18μm CMOS technology incorporating 26×10^6 transistors. The chip is designed to provide standard framing and mapping of 10/100/1000Mbit/s Ethernet, Resilient Packet Ring （RPR） and E1 traffics into protected Synchronous Digital Hierarchy （SDH） STM-1 transport payloads using hitless rate adaptation for optimum bandwidth utilization. It consumes 4W of power on average and utilizes 756 pin enhanced BGA package.