A low-power Rijndael S-Box based on pass transmission gate and composite field arithmetic

Using composite field arithmetic in Galois field can result in the compact Rijndael S-Box. However, the power con- sumption of this solution is too large to be used in resource-limited embedded systems. A full-custom hardware implementation of composite field S-Box is proposed for these targeted domains in this paper. The minimization of power consumption is implemented by optimizing the architecture of the composite field S-Box and using the pass transmission gate (PTG) to realize the logic functions of S-Box. Power simulations were performed using the netlist extracted from the layout. HSPICE simulation results indicated that the proposed S-Box achieves low power consumption of about 130 μW at 10 MHz using 0.25 μm/2.5 V technology, while the consumptions of the positive polarity reed-muller (PPRM) based S-Box and composite field S-Box based on the conventional CMOS logic style are about 240 μW and 420 μW, respectively. The simulations also showed that the presented S-Box obtains better low-voltage operating property, which is clearly relevant for applications like sensor nodes, smart cards and radio frequency identification (RFID) tags.

Low-power clock-less hardware implementation of the rijndael S-box for wireless sensor networks

The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor networks （WSN）. The design challenges for an efficient WSN mainly lie in two issues： power and security. The Rijindael algorithm is a candidate algorithm for encrypting data in WSN. The SubByte （S-box） transformation is the main building block of the Rijindael algorithm. It dominates the hardware complexity and power consumption of the Rijindael cryptographic engine. This article proposes a clock-less hardware implementation of the S-box. In this S-box, l） The composite field arithmetic in GF（（2^4））2 was used to implement the compact datapath circuit; 2） A high-efficiency latch controller was attained by utilizing the four-phase micropipeline. The presented hardware circuit is an application specific integrated circuit （ASIC） on 0.25 μm complementary mental oxide semiconductor （CMOS） process using three metal layers. The layout simulation results show that the proposed S-box offers low-power consumption and high speed with moderate area penalty. This study also proves that the clock-less design methodology can implement high- performance cryptographic intellectual property （IP） core for the wireless sensor node chips.