This article presents an M-algorithm （MA） decoder with 4 survival paths （MA4） for Institute of Electrical and Electronics Engineers （IEEE） 802.3ab 1000BASE-T gigabit Ethernet （GbE） transceiver. To fulfill the ...This article presents an M-algorithm （MA） decoder with 4 survival paths （MA4） for Institute of Electrical and Electronics Engineers （IEEE） 802.3ab 1000BASE-T gigabit Ethernet （GbE） transceiver. To fulfill the entire requirements, various methods were introduced to accelerate the MA4 decoder while retaining the desired high performance and low complexity. Optimized look-ahead architecture was employed to solve the critical path problem with minimal gate consumption. Symbol compression methods saved registers during pipeline stages. A sorting network accelerated the kernel sorting operation at low hardware cost by utilizing the special characteristics of MA4. Simulations and synthesis results show that the proposed decoder achieves 125 MHz clock frequency and l Gb/s throughput in 1.8 V 0.18μm standard cell complementary metal-oxide-semiconductor （CMOS） process. It achieves additional 0.4 dB coding gain over 14tap parallel decision feedback decoder （PDFD） with 39% area reduction.展开更多
基金the National Science Foundation for Creative Research Groups （60521002）Shanghai Natural Science Foundation （037062022）.
文摘This article presents an M-algorithm （MA） decoder with 4 survival paths （MA4） for Institute of Electrical and Electronics Engineers （IEEE） 802.3ab 1000BASE-T gigabit Ethernet （GbE） transceiver. To fulfill the entire requirements, various methods were introduced to accelerate the MA4 decoder while retaining the desired high performance and low complexity. Optimized look-ahead architecture was employed to solve the critical path problem with minimal gate consumption. Symbol compression methods saved registers during pipeline stages. A sorting network accelerated the kernel sorting operation at low hardware cost by utilizing the special characteristics of MA4. Simulations and synthesis results show that the proposed decoder achieves 125 MHz clock frequency and l Gb/s throughput in 1.8 V 0.18μm standard cell complementary metal-oxide-semiconductor （CMOS） process. It achieves additional 0.4 dB coding gain over 14tap parallel decision feedback decoder （PDFD） with 39% area reduction.
