We demonstrate a single-chip silicon optical single sideband (OSSB) modulator composed of a radio frequenc(RF) branch line coupler (BLC) and a silicon dual-parallel Mach–Zehnder modulator (DP-MZM).A co-design between...We demonstrate a single-chip silicon optical single sideband (OSSB) modulator composed of a radio frequenc(RF) branch line coupler (BLC) and a silicon dual-parallel Mach–Zehnder modulator (DP-MZM).A co-design between the BLC and the DP-MZM is implemented to improve the sideband suppression ratio (SSR).The modu lator has a modulation efficiency of V_(π)L_(π)~1.75 V·cm and a 3 dB electro-optical (EO) bandwidth of 48.7 GHz The BLC can generate a pair of RF signals with equal amplitudes and orthogonal phases at the optimal frequenc of 21 GHz.We prove through theoretical calculation and experiment that,although the BLC’s performance in terms of power balance and phase orthogonality deteriorates in a wider frequency range,high SSRs can be realized by adjusting relevant bias phases of the DP-MZM.With this technique,the undesired sidebands are completel suppressed below the noise floor in the frequency range from 15 GHz to 30 GHz when the chip operates in the ful carrier OSSB (FC-OSSB) mode.In addition,an SSR>35 dB and an carrier suppression ratio (CSR)>42 dB ar demonstrated at 21 GHz in the suppressed carrier OSSB (SC-OSSB) mode.展开更多
基金National Key Research and Development Program of China(2021YFB2800500)Scientific Project of Zhejiang Laboratory(2020LC0AD02)+1 种基金Science and Technology Program of Zhejiang Province(2022C01108)Science and Technology Innovation 2025 Major Project of Ningbo(2020Z021)
文摘We demonstrate a single-chip silicon optical single sideband (OSSB) modulator composed of a radio frequenc(RF) branch line coupler (BLC) and a silicon dual-parallel Mach–Zehnder modulator (DP-MZM).A co-design between the BLC and the DP-MZM is implemented to improve the sideband suppression ratio (SSR).The modu lator has a modulation efficiency of V_(π)L_(π)~1.75 V·cm and a 3 dB electro-optical (EO) bandwidth of 48.7 GHz The BLC can generate a pair of RF signals with equal amplitudes and orthogonal phases at the optimal frequenc of 21 GHz.We prove through theoretical calculation and experiment that,although the BLC’s performance in terms of power balance and phase orthogonality deteriorates in a wider frequency range,high SSRs can be realized by adjusting relevant bias phases of the DP-MZM.With this technique,the undesired sidebands are completel suppressed below the noise floor in the frequency range from 15 GHz to 30 GHz when the chip operates in the ful carrier OSSB (FC-OSSB) mode.In addition,an SSR>35 dB and an carrier suppression ratio (CSR)>42 dB ar demonstrated at 21 GHz in the suppressed carrier OSSB (SC-OSSB) mode.
