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Parallel Software-Based Self-Testing with Bounded Model Checking for Kilo-Core Networks-on-Chip
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作者 张颖 季鹏飞 +3 位作者 朱潘玮 zebo peng 李华伟 江建慧 《Journal of Computer Science & Technology》 SCIE EI CSCD 2023年第2期405-421,共17页
Online testing is critical to ensuring reliable operations of the next generation of supercomputers based on a kilo-core network-on-chip(NoC)interconnection fabric.We present a parallel software-based self-testing(SBS... Online testing is critical to ensuring reliable operations of the next generation of supercomputers based on a kilo-core network-on-chip(NoC)interconnection fabric.We present a parallel software-based self-testing(SBST)solution that makes use of the bounded model checking(BMC)technique to generate test sequences and parallel packets.In this method,the parallel SBST with BMC derives the leading sequence for each router’s internal function and detects all functionally-testable faults related to the function.A Monte-Carlo simulation algorithm is then used to search for the approximately optimum configuration of the parallel packets,which guarantees the test quality and minimizes the test cost.Finally,a multi-threading technology is used to ensure that the Monte-Carlo simulation can reach the approximately optimum configuration in a large random space and reduce the generating time of the parallel test.Experimental results show that the proposed method achieves a high fault coverage with a reduced test overhead.Moreover,by performing online testing in the functional mode with SBST,it effectively avoids the over-testing problem caused by functionally untestable turns in kilo-core NoCs. 展开更多
关键词 software-based self-testing(SBST) parallel test kilo-core networks-on-chip(NoCs) online testing
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Test Time Minimization for Hybrid BIST of Core-Based Systems
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作者 Gert Jervan Petru Eles +2 位作者 zebo peng Raimund Ubar Maksim Jenihhin 《Journal of Computer Science & Technology》 SCIE EI CSCD 2006年第6期907-912,共6页
This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are gen... This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off-line and stored in the system. In this paper we propose an iterative algorithm to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach cmploys a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions. 展开更多
关键词 SoC SELF-TEST hybrid BIST
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