基于0.7μm InP HBT工艺,设计了连续时间超高速宽带Σ-Δ模数转换器,其时钟采样率为10 GS/s.该模数转换器系统包括两级环路滤波器,一个2 bit ADC和一个2 bit DAC.为了方便测试,电路中还增加了2 bit DAC和输出缓冲电路.设计完成后的Σ-Δ...基于0.7μm InP HBT工艺,设计了连续时间超高速宽带Σ-Δ模数转换器,其时钟采样率为10 GS/s.该模数转换器系统包括两级环路滤波器,一个2 bit ADC和一个2 bit DAC.为了方便测试,电路中还增加了2 bit DAC和输出缓冲电路.设计完成后的Σ-ΔADC电路版图整体尺寸为1.58 mm×1.82 mm.电路后仿真结果表明:当时钟采样率为10 GS/s时,该ADC电路在输入信号频率为307 MHz时的带内无杂散动态范围为52.4 dB,信噪比为42.6 dB;在5 V电源电压下,电路的总功耗约为1.3 W.展开更多
A 12-bit 2.6 GS/s radio frequency digital to analog converter(RF DAC)based on 1 um GaAs heterojunction bipolar transistor(HBT)process is presented.The DAC integrates a 4:1 multiplexer to reduce the data rate of input ...A 12-bit 2.6 GS/s radio frequency digital to analog converter(RF DAC)based on 1 um GaAs heterojunction bipolar transistor(HBT)process is presented.The DAC integrates a 4:1 multiplexer to reduce the data rate of input ports,which greatly facilitates the application.DAC core adopts 4+8 segmented current steering structure.R-2R ladder network is used for 8 least significant bit(LSB)to realize binary current weighting and thermometer coding is used for 4 most significant bit(MSB).Return-to-zero(RZ)technology is used to expand the effective bandwidth of DAC output to the third Nyquist band.The proposed DAC has a better output power flatness and spurious-free dynamic range(SFDR).Compared to traditional DAC,measured results demonstrate that the output power of this RZ DAC is increased by 33 dB and the SFDR is enhanced by 27 dB near the second Nyquist band.展开更多
文摘基于0.7μm InP HBT工艺,设计了连续时间超高速宽带Σ-Δ模数转换器,其时钟采样率为10 GS/s.该模数转换器系统包括两级环路滤波器,一个2 bit ADC和一个2 bit DAC.为了方便测试,电路中还增加了2 bit DAC和输出缓冲电路.设计完成后的Σ-ΔADC电路版图整体尺寸为1.58 mm×1.82 mm.电路后仿真结果表明:当时钟采样率为10 GS/s时,该ADC电路在输入信号频率为307 MHz时的带内无杂散动态范围为52.4 dB,信噪比为42.6 dB;在5 V电源电压下,电路的总功耗约为1.3 W.
基金supported by Open Project of State Key Laboratory of Millimeter Waves (K201727)Open Project of National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology (KFJJ20170203)+1 种基金National Science Foundation (61571235, 61504065)Scientific Research Foundation of Nanjing University of Posts and Telecommunications (NUPTSF NY215138)
文摘A 12-bit 2.6 GS/s radio frequency digital to analog converter(RF DAC)based on 1 um GaAs heterojunction bipolar transistor(HBT)process is presented.The DAC integrates a 4:1 multiplexer to reduce the data rate of input ports,which greatly facilitates the application.DAC core adopts 4+8 segmented current steering structure.R-2R ladder network is used for 8 least significant bit(LSB)to realize binary current weighting and thermometer coding is used for 4 most significant bit(MSB).Return-to-zero(RZ)technology is used to expand the effective bandwidth of DAC output to the third Nyquist band.The proposed DAC has a better output power flatness and spurious-free dynamic range(SFDR).Compared to traditional DAC,measured results demonstrate that the output power of this RZ DAC is increased by 33 dB and the SFDR is enhanced by 27 dB near the second Nyquist band.
