High threshold voltage enhancement-mode GaN p-FET with Sirich LPCVD SiN_(x) gate insulator for high hole mobility

In this work,the GaN p-MISFET with LPCVD-SiN_(x) is studied as a gate dielectric to improve device performance.By changing the Si/N stoichiometry of SiN_(x),it is found that the channel hole mobility can be effectively enhanced with Si-rich SiN_(x) gate dielectric,which leads to a respectably improved drive current of GaN p-FET.The record high channel mobility of 19.4 cm2/(V∙s)was achieved in the device featuring an Enhancement-mode channel.Benefiting from the significantly improved channel mobility,the fabricated E-mode GaN p-MISFET is capable of delivering a decent-high current of 1.6 mA/mm,while simultaneously featuring a negative threshold-voltage(VTH)of–2.3 V(defining at a stringent criteria of 10μA/mm).The device also exhibits a well pinch-off at 0 V with low leakage current of 1 nA/mm.This suggests that a decent E-mode operation of the fabricated p-FET is obtained.In addition,the VTH shows excellent stability,while the threshold-voltage hysteresisΔVTH is as small as 0.1 V for a gate voltage swing up to–10 V,which is among the best results reported in the literature.The results indicate that optimizing the Si/N stoichiometry of LPCVD-SiN_(x) is a promising approach to improve the device performance of GaN p-MISFET.

Review of Technologies for High-Voltage Integrated Circuits

High-Voltage power Integrated Circuits(HVICs) are widely used to realize high-efficiency power conversions(e.g., AC/DC conversion), gate drivers for power devices and LED lighting, and so on. The Bipolar-CMOS-DMOS(BCD) process is proposed to fabricate devices with bipolar, CMOS, and DMOS modes, and thereby realize the single-chip integration of HVICs. The basic integrated technologies of HVICs include High-Voltage(HV) integrated device technology, HV interconnection technology, and isolation technology. The HV integrated device is the core of HVICs. The basic requirements of the HV integrated device are high breakdown voltage, low specific on-resistance,and process compatibility with low-voltage circuits. The REduced SURFace field(RESURF) technology and junction termination technology are developed to optimize the surface field of integration power devices and breakdown voltage. Furthermore, the ENhanced DIelectric layer Field(ENDIF) and REduced BULk Field(REBULF) technologies are proposed to optimize bulk fields. The double/triple RESURF technologies are further developed, and the superjunction concept is introduced to integrated power devices and to reduce the specific on-resistance. This work presents a comprehensive review of these technologies, including the innovation technologies of the authors’ group,such as ENDIF and REBULF, substrate termination technology prospective integrated technologies and HVICs in wide band gap semiconductor materials are also discussed.

Concept and design of super junction devices

The super junction（SJ） has been recognized as the ＂milestone＂ of the power MOSFET, which is the most important innovation concept of the voltage-sustaining layer（VSL）. The basic structure of the SJ is a typical junction-type VSL（J-VSL） with the periodic N and P regions. However, the conventional VSL is a typical resistance-type VSL（R-VSL） with only an N or P region. It is a qualitative change of the VSL from the R-VSL to the JVSL, introducing the bulk depletion to increase the doping concentration and optimize the bulk electric field of the SJ. This paper firstly summarizes the development of the SJ, and then the optimization theory of the SJ is discussed for both the vertical and the lateral devices, including the non-full depletion mode, the minimum specific on-resistance optimization method and the equivalent substrate model. The SJ concept breaks the conventional＂silicon limit＂ relationship of R_（on）∝V_B^（2.5）, showing a quasi-linear relationship of R_（on）∝V_B^（1.03）.