We present and propose a complete and iterative integrated-circuit and electro-magnetic（EM） co-design methodology and procedure for a low-voltage sub-1 GHz class-E PA.The presented class-E PA consists of the onchip ...We present and propose a complete and iterative integrated-circuit and electro-magnetic（EM） co-design methodology and procedure for a low-voltage sub-1 GHz class-E PA.The presented class-E PA consists of the onchip power transistor,the on-chip gate driving circuits,the off-chip tunable LC load network and the off-chip LC ladder low pass filter.The design methodology includes an explicit design equation based circuit components values＇ analysis and numerical derivation,output power targeted transistor size and low pass filter design,and power efficiency oriented design optimization.The proposed design procedure includes the power efficiency oriented LC network tuning,the detailed circuit/EM co-simulation plan on integrated circuit level,package level and PCB level to ensure an accurate simulation to measurement match and first pass design success.The proposed PA is targeted to achieve more than 15 dBm output power delivery and 40% power efficiency at 433 MHz frequency band with 1.5 V low voltage supply.The LC load network is designed to be off-chip for the purpose of easy tuning and optimization.The same circuit can be extended to all sub-1 GHz applications with the same tuning and optimization on the load network at different frequencies.The amplifier is implemented in 0.13 μm CMOS technology with a core area occupation of 400 μm by 300 μm.Measurement results showed that it provided power delivery of 16.42 dBm at antenna with efficiency of 40.6%.A harmonics suppression of 44 dBc is achieved,making it suitable for massive deployment of IoT devices.展开更多
基金supported by the National Natural Science Foundation of China(No.61574125)the Industry Innovation Project of Suzhou City of China(No.SYG201641)
文摘We present and propose a complete and iterative integrated-circuit and electro-magnetic（EM） co-design methodology and procedure for a low-voltage sub-1 GHz class-E PA.The presented class-E PA consists of the onchip power transistor,the on-chip gate driving circuits,the off-chip tunable LC load network and the off-chip LC ladder low pass filter.The design methodology includes an explicit design equation based circuit components values＇ analysis and numerical derivation,output power targeted transistor size and low pass filter design,and power efficiency oriented design optimization.The proposed design procedure includes the power efficiency oriented LC network tuning,the detailed circuit/EM co-simulation plan on integrated circuit level,package level and PCB level to ensure an accurate simulation to measurement match and first pass design success.The proposed PA is targeted to achieve more than 15 dBm output power delivery and 40% power efficiency at 433 MHz frequency band with 1.5 V low voltage supply.The LC load network is designed to be off-chip for the purpose of easy tuning and optimization.The same circuit can be extended to all sub-1 GHz applications with the same tuning and optimization on the load network at different frequencies.The amplifier is implemented in 0.13 μm CMOS technology with a core area occupation of 400 μm by 300 μm.Measurement results showed that it provided power delivery of 16.42 dBm at antenna with efficiency of 40.6%.A harmonics suppression of 44 dBc is achieved,making it suitable for massive deployment of IoT devices.
