Research on eigenstate current control technology of Flashbased FPGA

To solve the Flash-based FPGA in the manufacturing process,the ion implantation process will bring electrons into the floating gate of the P-channel Flash cell so that the Flash switch is in a weak conduction state,resulting in the Flash-based FPGA eigenstate current problem.In this paper,the mechanism of its generation is analyzed,and four methods are used includ-ing ultraviolet light erasing,high-temperature baking,X-ray irradiation,and circuit logic control.A comparison of these four methods can identify the circuit design by using circuit logic to control the path of the power supply that is the most suitable and reliable method to solve the Flash-based FPGA eigenstate current problem.By this method,the power-on current of 3.5 mil-lion Flash-based FPGA can be reduced to less than 0.3 A,and the chip can start normally.The function and performance of the chip can then be further tested and evaluated,which is one of the key technologies for developing Flash-based FPGA.

Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH

This paper proposes a kind of programmable logic element(PLE)based on Sense-Switch pFLASH technology.By programming Sense-Switch pFLASH,all three-bit look-up table(LUT3)functions,partial four-bit look-up table(LUT4)functions,latch functions,and d flip flop(DFF)with enable and reset functions can be realized.Because PLE uses a choice of operational logic(COOL)approach for the operation of logic functions,it allows any logic circuit to be implemented at any ratio of combinatorial logic to register.This intrinsic property makes it close to the basic application specific integrated circuit(ASIC)cell in terms of fine granularity,thus allowing ASIC-like cell-based mappers to apply all their optimization potential.By measuring Sense-Switch pFLASH and PLE circuits,the results show that the“on”state driving current of the Sense-Switch pFLASH is about 245.52μA,and that the“off”state leakage current is about 0.1 pA.The programmable function of PLE works normally.The delay of the typical combinatorial logic operation AND3 is 0.69 ns,and the delay of the sequential logic operation DFF is 0.65 ns,both of which meet the requirements of the design technical index.