Research on key technologies of edge cache in virtual data space across WAN

The authors of this paper have previously proposed the global virtual data space system (GVDS) to aggregate the scattered and autonomous storage resources in China’s national supercomputer grid (National Supercomputing Center in Guangzhou, National Supercomputing Center in Jinan, National Supercomputing Center in Changsha, Shanghai Supercomputing Center, and Computer Network Information Center in Chinese Academy of Sciences) into a storage system that spans the wide area network (WAN), which realizes the unified management of global storage resources in China. At present, the GVDS has been successfully deployed in the China National Grid environment. However, when accessing and sharing remote data in the WAN, the GVDS will cause redundant transmission of data and waste a lot of network bandwidth resources. In this paper, we propose an edge cache system as a supplementary system of the GVDS to improve the performance of upper-level applications accessing and sharing remote data. Specifically, we first designs the architecture of the edge cache system, and then study the key technologies of this architecture: the edge cache index mechanism based on double-layer hashing, the edge cache replacement strategy based on the GDSF algorithm, the request routing based on consistent hashing method, and the cluster member maintenance method based on the SWIM protocol. The experimental results show that the edge cache system has successfully implemented the relevant operation functions (read, write, deletion, modification, etc.) and is compatible with the POSIX interface in terms of function. Further, it can greatly reduce the amount of data transmission and increase the data access bandwidth when the accessed file is located at the edge cache system in terms of performance, i.e., its performance is close to the performance of the network file system in the local area network (LAN).

An efficient and fast polarity optimization approach for mixed polarity Reed-Muller logic circuits

Although the genetic algorithm has been widely used in the polarity optimization of mixed polarity Reed- Muller （MPRM） logic circuits, few studies have taken into account the polarity conversion sequence. In order to im- prove the efficiency of polarity optimization of MPRM logic circuits, we propose an efficient and fast polarity optimiza- tion approach （FPOA） considering the polarity conversion se- quence. The main idea behind the FPOA is that, firstly, the best polarity conversion sequence of the polarity set wait- ing for evaluation is obtained by using the proposed hybrid genetic algorithm （HGA）; secondly, each of polarity in the polarity set is converted according to the best polarity con- version sequence obtained by HGA. Our proposed FPOA is implemented in C and a comparative analysis has been pre- sented for MCNC benchmark circuits. The experimental re- suits show that for the circuits with more variables, the FPOA is highly effective in improving the efficiency of polarity op- timization of MPRM logic circuits compared with the tradi- tional polarity optimization approach which neglects the po- larity conversion sequence and the improved polarity opti- mization approach with heuristic technique.

EDOA: an efficient delay optimization approach for mixed-polarity Reed-Muller logic circuits under the unit delay model

Delay optimization has recently attracted signif-icant attention. However, few studies have focused on the delay optimization of mixed-polarity Reed-Muller (MPRM) logic circuits. In this paper, we propose an efficient delay op-timization approach (EDOA) for MPRM logic circuits under the unit delay model, which can derive an optimal MPRM logic circuit with minimum delay. First, the simplest MPRM expression with the fewest number of product terms is ob-tained using a novel Reed-Muller expression simplification approach (RMESA) considering don't-care terms. Second, a minimum delay decomposition approach based on a Huffman tree construction algorithm is utilized on the simplest MPRM expression. Experimental results on MCNC benchmark cir-cuits demonstrate that compared to the Berkeley SIS 1.2 and ABC, the EDOA can significantly reduce delay for most cir-cuits. Furthermore, for a few circuits, while reducing delay, the EDOA incurs an area penalty.

Fine-grained management of I/O optimizations based on workload characteristics

With the advent of new computing paradigms,parallel file systems serve not only traditional scientific computing applications but also non-scientific computing applications,such as financial computing,business,and public administration.Parallel file systems provide storage services for multiple applications.As a result,various requirements need to be met.However,parallel file systems usually provide a unified storage solution,which cannot meet specific application needs.In this paper,an extended tile handle scheme is proposed to deal with this problem.The original file handle is extended to record I/O optimization information,which allows file systems to specify optimizations for a file or directory based on workload characteristics.Therefore,fine-grained management of I/O optimizations can be achieved.On the basis of the extended file handle scheme,data prefetching and small file optimization mechanisms are proposed for parallel file systems.The experimental results show that the proposed approach improves the aggregate throughput of the overall system by up to 189.75%.