This paper presents a design scheme of SDRAM controller based on FPGA. The paper analyze the basic operation principle of SDRAM, and introduce the state machine and the arbitration mechanism. Simulation verification i...This paper presents a design scheme of SDRAM controller based on FPGA. The paper analyze the basic operation principle of SDRAM, and introduce the state machine and the arbitration mechanism. Simulation verification in QuartuslI development environment using Verilog language show that the system achieve high-speed data caching and transmission. The design method of each module and the realization process in the overall design is introduced in detail. The experimental results show that： the controller design is flexible, stable and reliable operation, low cost. can be used as IP core for the cache system in different SOC_展开更多
文摘This paper presents a design scheme of SDRAM controller based on FPGA. The paper analyze the basic operation principle of SDRAM, and introduce the state machine and the arbitration mechanism. Simulation verification in QuartuslI development environment using Verilog language show that the system achieve high-speed data caching and transmission. The design method of each module and the realization process in the overall design is introduced in detail. The experimental results show that： the controller design is flexible, stable and reliable operation, low cost. can be used as IP core for the cache system in different SOC_
