Aiming at the high computational complexity and low efficiency of the advanced residual prediction(ARP)algorithm in 3 dimension high-efficiency video coding(3D-HEVC),the relationship between the depth value and ARP is...Aiming at the high computational complexity and low efficiency of the advanced residual prediction(ARP)algorithm in 3 dimension high-efficiency video coding(3D-HEVC),the relationship between the depth value and ARP is analyzed.A fast ARP algorithm based on the depth value is proposed,which is implemented on the reconfigurable array processor developed by the project team.It uses a reconfigurable method to realize flexible switching between interview-ARP and tem-poral ARP.Experimental results show that while keeping the coding rate and the peak signal-to-noise ratio(PSNR)basically unchanged,the coding time of the six test sequences is reduced by 16.21%on average compared with HTM16.1.In contrast with non-reconfiguration,the average coding time is reduced by 52%,so the computational efficiency is improved.展开更多
The new encoding tools of high efficiency video coding(HEVC) make the interpolation operation more complex in motion compensation(MC) for better video compression, but impose higher requirements on the computational e...The new encoding tools of high efficiency video coding(HEVC) make the interpolation operation more complex in motion compensation(MC) for better video compression, but impose higher requirements on the computational efficiency and control logic of the hardware architecture. The reconfigurable array processor can take into consideration both the computational efficiency and flexible switching of algorithms very well. Through mining the data dependency and parallelism among interpolation operation, this paper presents a parallelization method based on the dynamic reconfigurable array processor proposed by the project team. The number of pixels loaded from the external memory is reduced significantly, by multiplexing the common data in the previous reference block and the current reference block. Flexible switching of variable block operation is realized by using dynamic reconfiguration mechanism. A 16×16 processor element(PE)’s array is used to dynamically process a 4×4-64×64 block size. The experimental results show that, the reference block update speed is increased by 39.9%. In the case of an array size of 16 PEs, the number of pixels processed in parallel reaches 16.展开更多
基金the National Natural Science Foundation of China(No.61834005,61772417,61634004,61602377)the Shaanxi Provincial Co-ordination Innovation Project of Science and Technology(No.2016KTZDGY02-04-02)。
文摘Aiming at the high computational complexity and low efficiency of the advanced residual prediction(ARP)algorithm in 3 dimension high-efficiency video coding(3D-HEVC),the relationship between the depth value and ARP is analyzed.A fast ARP algorithm based on the depth value is proposed,which is implemented on the reconfigurable array processor developed by the project team.It uses a reconfigurable method to realize flexible switching between interview-ARP and tem-poral ARP.Experimental results show that while keeping the coding rate and the peak signal-to-noise ratio(PSNR)basically unchanged,the coding time of the six test sequences is reduced by 16.21%on average compared with HTM16.1.In contrast with non-reconfiguration,the average coding time is reduced by 52%,so the computational efficiency is improved.
基金supported by the National Natural Science Foundation of China(61834005,61772417,61802304,61874087,61602377,61634004,61272120)the Shaanxi Province Coordination Innovation Project of Science and Technology(2016KTZDGY02-04-02)+1 种基金the Shaanxi Provincial Key R&D Plan(2017GY-060)Shaanxi International Science and Technology Cooperation Program(2018KW-006)。
文摘The new encoding tools of high efficiency video coding(HEVC) make the interpolation operation more complex in motion compensation(MC) for better video compression, but impose higher requirements on the computational efficiency and control logic of the hardware architecture. The reconfigurable array processor can take into consideration both the computational efficiency and flexible switching of algorithms very well. Through mining the data dependency and parallelism among interpolation operation, this paper presents a parallelization method based on the dynamic reconfigurable array processor proposed by the project team. The number of pixels loaded from the external memory is reduced significantly, by multiplexing the common data in the previous reference block and the current reference block. Flexible switching of variable block operation is realized by using dynamic reconfiguration mechanism. A 16×16 processor element(PE)’s array is used to dynamically process a 4×4-64×64 block size. The experimental results show that, the reference block update speed is increased by 39.9%. In the case of an array size of 16 PEs, the number of pixels processed in parallel reaches 16.
