Cell Mapping for Nanohybrid Circuit Architecture Using Genetic Algorithm

Nanoelectronics constructed by nanoscale devices seems promising for the advanced development of integrated circuits （ICs）. However, the lack of computer aided design （CAD） tools seriously hinders its development and applications. To investigate the cell mapping task in CAD flow, we present a genetic algorithm （GA） based method for Cmos/nanowire/MOLecular hybrid （CMOL）, which is a nanohybrid circuit architecture. By designing several crossover operators and analyzing their performance, an efficient crossover operator is proposed. Combining a mutation operator, a GA based algorithm is presented and tested on the International Symposium on Circuits and Systems （ISCAS） benchmarks. The results show that the proposed method not only can obtain better area utilization and smaller delay, but also can handle larger benchmarks with CPU time improvement compared with the published methods.

Inversion Optimization Strategy Based on Primitives with Complement Attributes

Inverters or logic primitives that have complement attributes are essential to building a logical complement system.NAND and NOR operations which have complement attributes are of high interest for complementary metal-oxidesemiconductor(CMOS)technology,as they can be easily implemented in transistors.Different from the logic models used in standard CMOS,several nano-emerging technologies,such as quantum-dot cellular automata(QCA)and spin torque majority gates,are in favor of realizing a majority voter function but imposing difficulties in implementing inversions.Previous studies pay lots of effort in optimizing the number of inverters in logic representations,whereas the mapping using primitives with complement attributes is not a major concern.In this paper,we establish a technology mapping method from logic representations to nanotechnology primitives by considering NAND-NOR-Inverter(NNI)and exclusive-NOR(XNOR)operations.We adopt XOR-Majority Graph(XMG)as a logic representation.The proposed mapping method is evaluated using the QCA technology.Experimental results over EPFL benchmark suites show we achieve 11.77%and 30.13%reductions in the area and the number of inverters,respectively.

Defect-Tolerant Mapping of CMOL Circuit Targeting Delay Optimization

In view of the significant number of defective nanodevices in the Cmos/nanowire/MOLecular hybrid(CMOL)circuit,defect-tolerant mapping is an essential step to achieve correct logic operations in defective CMOL circuits.However,less effort has been made to improve circuit delay by defect-tolerant strategies.In this paper,the factors affecting the delay of mapped circuits are analyzed,and the path-tree based defect-tolerant mapping method for the delay optimization is proposed.From the logic-domain,the terminology of the path tree is presented,and the logic circuit is first partitioned into multiple path trees.Then,the mapping areas in the physic-domain are pre-planned for(near)critical path trees.During the mapping process,the specific mapping modes and an updating strategy are formulated to map the path trees:inputs are mapped based on input sorting;(near)critical path trees are mapped with priority,while the others are mapped in a hierarchical way.Finally,an improved tabu search algorithm is employed to verify the validity of the proposed defect-tolerant mapping method.Experimental evaluations on the ISCAS benchmarks show that the proposed method can reduce circuit delay by 15.22%.