Using Altera＇s Quartus II, Nios II IDE and Sopc Builder development tools, the proton precession magnetometer principle host hardware platform is designed in a cyclone II series FPGA chip （EP2C35）. The proton prece...Using Altera＇s Quartus II, Nios II IDE and Sopc Builder development tools, the proton precession magnetometer principle host hardware platform is designed in a cyclone II series FPGA chip （EP2C35）. The proton precession magnetometer principle host core circuit＇s single-chip system-logic design is achieved by building and configuring the Nios II soft-core processor, developing the IO interface and sensor control circuits, programming some hardware units＇ VHDL code, for example the equal precision cymometer and the DPLL. Through researching the embedded operating system configuration technology and building the NIOS II soft-core processor＇s μClinux cross-compile environment, the μClinux system is transplanted to the NIOS II environment. Another important task is writing the device drivers＇ and user programs＇ code. Through these work, the design realize the host function and achieve the expected target.展开更多
基金supported by Public Benefit Research Sector (No.H200708045)Basic R&D Operations Special (Nos.ZDJ2008-01 and J220780804)
文摘Using Altera＇s Quartus II, Nios II IDE and Sopc Builder development tools, the proton precession magnetometer principle host hardware platform is designed in a cyclone II series FPGA chip （EP2C35）. The proton precession magnetometer principle host core circuit＇s single-chip system-logic design is achieved by building and configuring the Nios II soft-core processor, developing the IO interface and sensor control circuits, programming some hardware units＇ VHDL code, for example the equal precision cymometer and the DPLL. Through researching the embedded operating system configuration technology and building the NIOS II soft-core processor＇s μClinux cross-compile environment, the μClinux system is transplanted to the NIOS II environment. Another important task is writing the device drivers＇ and user programs＇ code. Through these work, the design realize the host function and achieve the expected target.
