A novel structure for a charge pump circuit is proposed, in which the charge-pump （CP） current can adaptively regulated according to phase-locked loops （PLL） frequency synthesis demand. The current follow technolo...A novel structure for a charge pump circuit is proposed, in which the charge-pump （CP） current can adaptively regulated according to phase-locked loops （PLL） frequency synthesis demand. The current follow technology is used to make perfect current matching characteristics, and the two differential inverters are implanted to increase the speed of charge pump and decrease output spur due to theory of low voltage difference signal. Simulation results, with 1st silicon 0. 25μm 2. 5 V complementary metal-oxide-semiconductor （CMOS） mixed-signal process, show the good current matching characteristics regardless of the charge pump output voltages.展开更多
A self-balanced charge pump （CP） with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25μm 1P5M complementary metal oxide semiconductor...A self-balanced charge pump （CP） with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25μm 1P5M complementary metal oxide semiconductor （CMOS） process with a 2.5 V supply voltage, HSPICE simulation shows that even if the mismatch of phase/frequency detector （PFD） was beyond 10%, the charge pump could still keep nearly zero phase error, Incorporated fast lock circuit can shorten start-up time to below 300 ns.展开更多
This paper takes full advantages of the I-V transconductance characteristics of metal-oxide semiconductor field effect transistor （MOSFET） operating in the subthreshold region and the enhancement pre-regulator techn...This paper takes full advantages of the I-V transconductance characteristics of metal-oxide semiconductor field effect transistor （MOSFET） operating in the subthreshold region and the enhancement pre-regulator technique with the high gain negative feedback loop. The proposed reference circuit, designed with the SMIC 0.18 μm standard complementary metal-oxide semiconductor （CMOS） logic process technology, exhibits a stable current of about 1.701 μA with much low temperature coefficient （TC） of 2.5×10^-4μA/℃ in the temperature range of-40 to 150℃ at 1.5 V supply voltage, and also achieves a best PSRR over a broad frequency. The PSRR is about - 126 dB at DC frequency and remains -92 dB at the frequency higher 100 MHz. Moreover the proposed reference circuit operates stably at the supply voltage higher 1.2 V and has good process compatibility.展开更多
A 3.5 times PLL clock frequency multiplier for low voltage different signal （LVDS） driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator （...A 3.5 times PLL clock frequency multiplier for low voltage different signal （LVDS） driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator （VCO） is designed with the aid of frequency ranges reuse technology. The circuit is implemented using 1st Silicon 0.25 μm mixed-signal complementary metal-oxide-semiconductor （CMOS） process. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time .展开更多
In the complex multicore chip system,network on-chip(NoC)is viewed as a kind of system interconnection that can substitute the traditional interconnect networks,which will improve the system performance and communicat...In the complex multicore chip system,network on-chip(NoC)is viewed as a kind of system interconnection that can substitute the traditional interconnect networks,which will improve the system performance and communication efficiency.With regard to the complex and large scale NoC,simple and efficient routing nodes are the critical factors to achieve low-cost and low-congestion communication performance.This paper proposes an unbuffered switch architecture and makes detailed analysis of the mechanism of buffer in the switch architecture.According to the simulation results,the S-mesh using the unbuffered switch architecture is better in terms of the optimal performance in message latency than some typical NoC architectures,such as 2D-mesh,Fat-tree,Butterfly,Octagon and so on.The synthesis results of design compiler indicate that the unbuffered switch has obvious advantages of achieving cost and operating speed for the chips.展开更多
To obtain a low-power and compact implementation of the advanced encryption standard(AES)S-box,an asynchronous pipeline architecture over composite field arithmetic was proposed in this paper.Inthe presented S-box,som...To obtain a low-power and compact implementation of the advanced encryption standard(AES)S-box,an asynchronous pipeline architecture over composite field arithmetic was proposed in this paper.Inthe presented S-box,some improvements were made as follows.(1)Level-sensitive latches were insertedin data path to block the propagation Of the dynamic hazards,which lowered the power of data path cir-cuit.(2)Operations of latches were controlled by latch controllers based on presented asynchronous se-quence element:LC-element,which utilized static asymmetric C-element to construct a simple and pow-er-efficient circuit structure.(3)Implementation of the data path circuit was a semi-custom standard-cellcircuit on 0.25μm complementary mental oxide semiconductor(CMOS)process;and the full-custom de-sign methodology was adopted in the handshake circuit design.Experimental results show that the result-ing circuit achieves nearly 46% improvement with moderate area penalty(11.7%)compared with the re-lated composite field S-box in power performance.The presented S-box circuit can be a hardware intelli-gent property(IP)embedded in the targeted systems such as wireless sensor networks(WSN),smart-cams and radio frequency identification(RFID).展开更多
QLC（Quad-Level Cell） NAND flash will be one of the future technologies for next generation memory chip after three-dimensional（3D） TLC（Triple-Level Cell） stacked NAND flash. In QLC device, data errors will easil...QLC（Quad-Level Cell） NAND flash will be one of the future technologies for next generation memory chip after three-dimensional（3D） TLC（Triple-Level Cell） stacked NAND flash. In QLC device, data errors will easily occur because of 2~4 data levels in the limited voltage range. This paper studies QLC NAND technology which is 4 bits per cell. QLC programming methods based on 16 voltage levels and reading method based on ＂half-change＂ Gray coding are researched. Because of the probable error impact of QLC NAND cell＇s voltage change, the solution of generating the soft information after XOR（exclusive OR） the soft bits by internal read mechanism is presented for Low-Density Parity-Check（LDPC） Belief Propagation（BP） decoding in QLC design for its system level application.展开更多
NAND flash chips have been innovated from two-dimension （2D） design which is based on planar NAND cells to three-dimension （3D） design which is based on vertical NAND cells. Two types of NAND flash technologies-ch...NAND flash chips have been innovated from two-dimension （2D） design which is based on planar NAND cells to three-dimension （3D） design which is based on vertical NAND cells. Two types of NAND flash technologies-charge-trap （CT） and floating-gate （FG） are presented in this paper to introduce NAND flash designs in detail. The physical characteristics of CT-based and FG-based 3D NAND flashes are analyzed. Moreover, the advantages and disadvantages of these two technologies in architecture, manufacture, interference and reliability are studied and compared.展开更多
This paper presents a wide supply voltage range, high speed true random number generator（TRNG） based on ring oscillators, which have different prime number of inverters. And a simple Von Neumann corrector as post pr...This paper presents a wide supply voltage range, high speed true random number generator（TRNG） based on ring oscillators, which have different prime number of inverters. And a simple Von Neumann corrector as post processing is also realized to improve data randomness. Prototypes have been implemented and fabricated in 0.18 μm complementary metal oxide semiconductor（CMOS） technology with a wide range of supply voltage from 1.8 V to 3.6 V. The circuit occupies 4 500 μm2, and dissipates minimum 160 μW of power with sampling frequency of 20 MHz. Output bit rate range is from 100 kbit/s to 20 Mbit/s. Statistical test results, which were achieved from the die Hard battery of tests, demonstrate that output random numbers have a well characteristic of randomness.展开更多
文摘A novel structure for a charge pump circuit is proposed, in which the charge-pump （CP） current can adaptively regulated according to phase-locked loops （PLL） frequency synthesis demand. The current follow technology is used to make perfect current matching characteristics, and the two differential inverters are implanted to increase the speed of charge pump and decrease output spur due to theory of low voltage difference signal. Simulation results, with 1st silicon 0. 25μm 2. 5 V complementary metal-oxide-semiconductor （CMOS） mixed-signal process, show the good current matching characteristics regardless of the charge pump output voltages.
基金Supported by the National High Technology Re-search and Development Programof China (2004AA122310)
文摘A self-balanced charge pump （CP） with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25μm 1P5M complementary metal oxide semiconductor （CMOS） process with a 2.5 V supply voltage, HSPICE simulation shows that even if the mismatch of phase/frequency detector （PFD） was beyond 10%, the charge pump could still keep nearly zero phase error, Incorporated fast lock circuit can shorten start-up time to below 300 ns.
基金Supported by the National Natural Science Foundation of China (60376019)
文摘This paper takes full advantages of the I-V transconductance characteristics of metal-oxide semiconductor field effect transistor （MOSFET） operating in the subthreshold region and the enhancement pre-regulator technique with the high gain negative feedback loop. The proposed reference circuit, designed with the SMIC 0.18 μm standard complementary metal-oxide semiconductor （CMOS） logic process technology, exhibits a stable current of about 1.701 μA with much low temperature coefficient （TC） of 2.5×10^-4μA/℃ in the temperature range of-40 to 150℃ at 1.5 V supply voltage, and also achieves a best PSRR over a broad frequency. The PSRR is about - 126 dB at DC frequency and remains -92 dB at the frequency higher 100 MHz. Moreover the proposed reference circuit operates stably at the supply voltage higher 1.2 V and has good process compatibility.
基金Supported by the National Key Pre-Research Project of China (413010701-3)
文摘A 3.5 times PLL clock frequency multiplier for low voltage different signal （LVDS） driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator （VCO） is designed with the aid of frequency ranges reuse technology. The circuit is implemented using 1st Silicon 0.25 μm mixed-signal complementary metal-oxide-semiconductor （CMOS） process. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time .
基金Supported by the National High Technology Research and Development Program of China(No.2009AA01Z105)the Ministry of EducationIntel Special Foundation for Information Technology(No.MOE-INTEL-08-05)the Postdoctoral Science Foundation of China(No.20080440942,200902432)
文摘In the complex multicore chip system,network on-chip(NoC)is viewed as a kind of system interconnection that can substitute the traditional interconnect networks,which will improve the system performance and communication efficiency.With regard to the complex and large scale NoC,simple and efficient routing nodes are the critical factors to achieve low-cost and low-congestion communication performance.This paper proposes an unbuffered switch architecture and makes detailed analysis of the mechanism of buffer in the switch architecture.According to the simulation results,the S-mesh using the unbuffered switch architecture is better in terms of the optimal performance in message latency than some typical NoC architectures,such as 2D-mesh,Fat-tree,Butterfly,Octagon and so on.The synthesis results of design compiler indicate that the unbuffered switch has obvious advantages of achieving cost and operating speed for the chips.
基金the National High Technology Research and Development Programme of China(Grant No2006AA01Z226)the Project(Grant No2006Z001B)the Scientific Research Foundation of Huazhong University of Science and Technology
文摘To obtain a low-power and compact implementation of the advanced encryption standard(AES)S-box,an asynchronous pipeline architecture over composite field arithmetic was proposed in this paper.Inthe presented S-box,some improvements were made as follows.(1)Level-sensitive latches were insertedin data path to block the propagation Of the dynamic hazards,which lowered the power of data path cir-cuit.(2)Operations of latches were controlled by latch controllers based on presented asynchronous se-quence element:LC-element,which utilized static asymmetric C-element to construct a simple and pow-er-efficient circuit structure.(3)Implementation of the data path circuit was a semi-custom standard-cellcircuit on 0.25μm complementary mental oxide semiconductor(CMOS)process;and the full-custom de-sign methodology was adopted in the handshake circuit design.Experimental results show that the result-ing circuit achieves nearly 46% improvement with moderate area penalty(11.7%)compared with the re-lated composite field S-box in power performance.The presented S-box circuit can be a hardware intelli-gent property(IP)embedded in the targeted systems such as wireless sensor networks(WSN),smart-cams and radio frequency identification(RFID).
文摘QLC（Quad-Level Cell） NAND flash will be one of the future technologies for next generation memory chip after three-dimensional（3D） TLC（Triple-Level Cell） stacked NAND flash. In QLC device, data errors will easily occur because of 2~4 data levels in the limited voltage range. This paper studies QLC NAND technology which is 4 bits per cell. QLC programming methods based on 16 voltage levels and reading method based on ＂half-change＂ Gray coding are researched. Because of the probable error impact of QLC NAND cell＇s voltage change, the solution of generating the soft information after XOR（exclusive OR） the soft bits by internal read mechanism is presented for Low-Density Parity-Check（LDPC） Belief Propagation（BP） decoding in QLC design for its system level application.
文摘NAND flash chips have been innovated from two-dimension （2D） design which is based on planar NAND cells to three-dimension （3D） design which is based on vertical NAND cells. Two types of NAND flash technologies-charge-trap （CT） and floating-gate （FG） are presented in this paper to introduce NAND flash designs in detail. The physical characteristics of CT-based and FG-based 3D NAND flashes are analyzed. Moreover, the advantages and disadvantages of these two technologies in architecture, manufacture, interference and reliability are studied and compared.
基金supported by the National Natural Science Foundation of China (61376031)
文摘This paper presents a wide supply voltage range, high speed true random number generator（TRNG） based on ring oscillators, which have different prime number of inverters. And a simple Von Neumann corrector as post processing is also realized to improve data randomness. Prototypes have been implemented and fabricated in 0.18 μm complementary metal oxide semiconductor（CMOS） technology with a wide range of supply voltage from 1.8 V to 3.6 V. The circuit occupies 4 500 μm2, and dissipates minimum 160 μW of power with sampling frequency of 20 MHz. Output bit rate range is from 100 kbit/s to 20 Mbit/s. Statistical test results, which were achieved from the die Hard battery of tests, demonstrate that output random numbers have a well characteristic of randomness.
