Time-interleaved structure can promote the equivalent processing speed of a digital signal processing system. An improved time-interleaved error feedback delta sigma modulator( TI-EF-DSM)for digital transmitter applic...Time-interleaved structure can promote the equivalent processing speed of a digital signal processing system. An improved time-interleaved error feedback delta sigma modulator( TI-EF-DSM)for digital transmitter application is presented in this paper. Two TI-EF-DSMs are compared,one is a conventional directly implemented and the other is the improved. The processing speed of the proposed two-channel improved time-interleaved error feedback delta sigma modulator( ITI-EF-DSM) is higher than the conventional directly implemented TI-EF-DSM for shortened critical path. A digital transmitter based on the ITI-EF-DSM is implemented on field progrmmable gate array( FPGA). The long term evolution( LTE) signals with different bandwidths of 5 MHz,10 MHz and 20 MHz are used as the signal source to evaluate the transmitter. The achieved SNR is 41 dB for the 20 MHz LTE signal with the processing clock of only 184 MHz.展开更多
A new digital transmitter based on delta sigma modulator( DSM) with bus-splitting is presented in this paper. The second order low pass error-feedback delta sigma modulator( EF-DSM) is focused. The signal to noise rat...A new digital transmitter based on delta sigma modulator( DSM) with bus-splitting is presented in this paper. The second order low pass error-feedback delta sigma modulator( EF-DSM) is focused. The signal to noise ratio( SNR) of the EF-DSM is derived for different bus-splitting bits.Following the EF-DSM,a multi-bit digital up mixer is used for carrier frequency transform. In order to validate the theory of bus-splitting,two types of transmitters are implemented on FPGA for comparison,in which one is with non-bus-splitting and the other is with bus-splitting. The FPGA implemented transmitter with bus-splitting promotes the maximum operation speed by 39%,and reduces hardware consumptions more than 16%. Both single tone and orthogonal frequency division multiplexing( OFDM) signal source are used to evaluate the proposed transmitter.展开更多
This paper presents a reconfigurable RF front-end for multi-mode multi-standard(MMMS) applications. The designed RF front-end is fabricated in 0.18 μm RF CMOS technology. The low noise characteristic is achieved by t...This paper presents a reconfigurable RF front-end for multi-mode multi-standard(MMMS) applications. The designed RF front-end is fabricated in 0.18 μm RF CMOS technology. The low noise characteristic is achieved by the noise canceling technique while the bandwidth is enhanced by gate inductive peaking technique. Measurement results show that, while the input frequency ranges from 100 MHz to 2.9 GHz, the proposed reconfigurable RF front-end achieves a controllable voltage conversion gain(VCG) from 18 dB to 39 dB. The measured maximum input third intercept point(IIP3) is-4.9 dBm and the minimum noise figure(NF) is 4.6 dB. The consumed current ranges from 16 mA to 26.5 mA from a 1.8 V supply voltage. The chip occupies an area of 1.17 mm^2 including pads.展开更多
An adjustable mixer for surface acoustic wave( SAW)-less radio frequency( RF) front-end is presented in this paper. Through changing the bias voltage,the presented mixer with reconfigurable voltage conversion gain( VC...An adjustable mixer for surface acoustic wave( SAW)-less radio frequency( RF) front-end is presented in this paper. Through changing the bias voltage,the presented mixer with reconfigurable voltage conversion gain( VCG) is suitable for multi-mode multi-standard( MMMS) applications. An equivalent local oscillator( LO) frequency-tunable high-Q band-pass filter( BPF) at low noise amplifier( LNA) output is used to reject the out-of-band interference signals. Base-band( BB) capacitor of the mixer is variable to obtain 15 kinds of intermediate frequency( IF) bandwidth( BW). The proposed passive mixer with LNA is implemented in TSMC 0. 18μm RF CMOS process and operates from 0. 5 to 2. 5 GHz with measured maximum out-of-band rejection larger than 40 d B. The measured VCG of the front-end can be changed from 5 to 17 d B; the maximum input intercept point( IIP3) is0 d Bm and the minimum noise figure( NF) is 3. 7 d B. The chip occupies an area of 0. 44 mm^2 including pads.展开更多
In this paper,detailed models of 14-bit 100 MS/s pipelined analog-to-digital converter( ADC)are presented. In order to help design of ADC system,blocks for pipelined ADC and disturbance sources are carefully analyzed....In this paper,detailed models of 14-bit 100 MS/s pipelined analog-to-digital converter( ADC)are presented. In order to help design of ADC system,blocks for pipelined ADC and disturbance sources are carefully analyzed. Critical parameters,such as capacitor mismatch,clock jitter are proposed and simulated. The pipelined ADC system is divided into five parts,clock generator,sample and hold( S/H) circuit,multiplying digital-to-analog converters( MDAC),backend,and digital correction. These blocks introduce several interferences,which attenuate performance of pipelined ADC severely. Modeling and simulations of these disturbance sources are presented particularly. A new model of S/H is introduced. Results derived from simulations can supervise design and optimization of the ADC system.展开更多
A fully integrated wideband voltage-controlled-oscillator(VCO) based on current-reused topology is presented. The overall scheme contains two sub-VCOs, which are controlled by a switch to cover a wide output frequency...A fully integrated wideband voltage-controlled-oscillator(VCO) based on current-reused topology is presented. The overall scheme contains two sub-VCOs, which are controlled by a switch to cover a wide output frequency range. Fabricated in TSMC 65 nm CMOS technology, the measured output frequency of the VCO ranges from 3.991 GHz to 9.713 GHz,achieving a tuning range of 83.5%. And the worst and best phase noise at 1 MHz offset are-93.09 dBc/Hz and-111.97 dBc/Hz, respectively. With a 1.2 V supply voltage, the VCO core consumes a current of 3.7-5.1 mA across the entire frequency range. The chip area is 0.51 mm^2, including the pads. Moreover, the proposed VCO provides a figure-of-merit-with-tuning-range(FOM_T) of-191 dBc/Hz to-197 dBc/Hz.展开更多
A new method of improving speed of latch-type comparators with preamplifier is presented. It investigates the relationship of current and transistor scales which affect delay time(tp) in latch. It applies a mathematic...A new method of improving speed of latch-type comparators with preamplifier is presented. It investigates the relationship of current and transistor scales which affect delay time(tp) in latch. It applies a mathematical model to optimize latch design. A figure of merit indicates that ratio Ipmos/Inmos is 0.25 in latch leading to optimal delay time. In order to suppress offset of latch, the cross-coupled loading, adopted in telescope preamplifier, which enhances the gain, is well analyzed and designed. The chip is fabricated in 0.18 μm CMOS technology. The delay time of latch comparator is less than 400 ps @500 MHz. The offset of comparator is estimated through Monte Carlo simulation. And power consumption is only 144 W under 1.8 V power supply. Results of on wafer testing are presented at the end of the paper. The chip occupies an area of 0.66×0.55 mm^2 and drains current of 80 μA.展开更多
A fractional frequency divider based on phase switching and negative feedback delta-sigma modulator(NF-DSM) is presented. The phase switching circuit, realized by switching 8 signals generated by a divider-by-4 circui...A fractional frequency divider based on phase switching and negative feedback delta-sigma modulator(NF-DSM) is presented. The phase switching circuit, realized by switching 8 signals generated by a divider-by-4 circuit, is adopted to reduce the frequency division step. The NF-DSM, which can obtain smooth output spectra, is proposed to generate the fractional part of the division ratio, moreover, the integer part of the division ratio is realized by a divider-by-2/3 circuit chain. Fabricated in TSMC 0.18 μm RF CMOS technology, the fractional frequency divider achieves a measured operation frequency from 0.5 GHz to 8 GHz. With a 1.8 V supply voltage, the maximum current consumption of the whole divider is 17.5 mA, and the chip area is 0.58 mm^2, including the pads.展开更多
This paper presents a wideband low noise amplifier (LNA) for multi-standard radio applications. The low noise characteristic is achieved by the noise-canceling technique while the bandwidth is enhanced by gate- indu...This paper presents a wideband low noise amplifier (LNA) for multi-standard radio applications. The low noise characteristic is achieved by the noise-canceling technique while the bandwidth is enhanced by gate- inductive-peaking technique. High-frequency noise performance is consequently improved by the flattened gain over the entire operating frequency band. Fabricated in 0.18 μm CMOS process, the LNA achieves 2.5 GHz of -3 dB bandwidth and 16 dB of gain. The gain variation is within 4-0.8 dB from 300 MHz to 2.2 GHz. The measured noise figure (NF) and average IIP3 are 3.4 dB and -2 dBm, respectively. The proposed LNA occupies 0.39 mm2 core chip area. Operating at 1.8 V, the LNA drains a current of 11.7 mA.展开更多
基金Supported by the National Natural Science Foundation of China(No.61674037)the National Key Research and Development Program of China(No.2016YFC0800400)+2 种基金the Priority Academic Program Development of Jiangsu Higher Education Institutionsthe National Power Grid Corp Science and Technology Project(No.SGTYHT/16-JS-198)the State Grid Nanjing Power Supply Company Project(No.1701052)
文摘Time-interleaved structure can promote the equivalent processing speed of a digital signal processing system. An improved time-interleaved error feedback delta sigma modulator( TI-EF-DSM)for digital transmitter application is presented in this paper. Two TI-EF-DSMs are compared,one is a conventional directly implemented and the other is the improved. The processing speed of the proposed two-channel improved time-interleaved error feedback delta sigma modulator( ITI-EF-DSM) is higher than the conventional directly implemented TI-EF-DSM for shortened critical path. A digital transmitter based on the ITI-EF-DSM is implemented on field progrmmable gate array( FPGA). The long term evolution( LTE) signals with different bandwidths of 5 MHz,10 MHz and 20 MHz are used as the signal source to evaluate the transmitter. The achieved SNR is 41 dB for the 20 MHz LTE signal with the processing clock of only 184 MHz.
基金Supported by the National Natural Science Foundation of China(No.61674037)National Key Research and Development Program of China(No.2016YFC0800400)+1 种基金the Priority Academic Program Development of Jiangsu Higher Education Institutionsthe National Power Grid Corp Science and Technology Project(No.SGTYHT/16-JS-198)
文摘A new digital transmitter based on delta sigma modulator( DSM) with bus-splitting is presented in this paper. The second order low pass error-feedback delta sigma modulator( EF-DSM) is focused. The signal to noise ratio( SNR) of the EF-DSM is derived for different bus-splitting bits.Following the EF-DSM,a multi-bit digital up mixer is used for carrier frequency transform. In order to validate the theory of bus-splitting,two types of transmitters are implemented on FPGA for comparison,in which one is with non-bus-splitting and the other is with bus-splitting. The FPGA implemented transmitter with bus-splitting promotes the maximum operation speed by 39%,and reduces hardware consumptions more than 16%. Both single tone and orthogonal frequency division multiplexing( OFDM) signal source are used to evaluate the proposed transmitter.
基金Supported by the National Nature Science Foundation of China(No.61674037)the Priority Academic Program Development of Jiangsu Higher Education Institutions,the National Power Grid Corp Science and Technology Project(No.SGTYHT/16-JS-198)the State Grid Nanjing Power Supply Company Project(No.1701052)
文摘This paper presents a reconfigurable RF front-end for multi-mode multi-standard(MMMS) applications. The designed RF front-end is fabricated in 0.18 μm RF CMOS technology. The low noise characteristic is achieved by the noise canceling technique while the bandwidth is enhanced by gate inductive peaking technique. Measurement results show that, while the input frequency ranges from 100 MHz to 2.9 GHz, the proposed reconfigurable RF front-end achieves a controllable voltage conversion gain(VCG) from 18 dB to 39 dB. The measured maximum input third intercept point(IIP3) is-4.9 dBm and the minimum noise figure(NF) is 4.6 dB. The consumed current ranges from 16 mA to 26.5 mA from a 1.8 V supply voltage. The chip occupies an area of 1.17 mm^2 including pads.
基金Supported by the National Basic Research Program of China(No.2010CB327404)the Priority Academic Program Development of Jiangsu Higher Education Institutions
文摘An adjustable mixer for surface acoustic wave( SAW)-less radio frequency( RF) front-end is presented in this paper. Through changing the bias voltage,the presented mixer with reconfigurable voltage conversion gain( VCG) is suitable for multi-mode multi-standard( MMMS) applications. An equivalent local oscillator( LO) frequency-tunable high-Q band-pass filter( BPF) at low noise amplifier( LNA) output is used to reject the out-of-band interference signals. Base-band( BB) capacitor of the mixer is variable to obtain 15 kinds of intermediate frequency( IF) bandwidth( BW). The proposed passive mixer with LNA is implemented in TSMC 0. 18μm RF CMOS process and operates from 0. 5 to 2. 5 GHz with measured maximum out-of-band rejection larger than 40 d B. The measured VCG of the front-end can be changed from 5 to 17 d B; the maximum input intercept point( IIP3) is0 d Bm and the minimum noise figure( NF) is 3. 7 d B. The chip occupies an area of 0. 44 mm^2 including pads.
基金Supported by the National Basic Research Program of China(No.2010CB327404)
文摘In this paper,detailed models of 14-bit 100 MS/s pipelined analog-to-digital converter( ADC)are presented. In order to help design of ADC system,blocks for pipelined ADC and disturbance sources are carefully analyzed. Critical parameters,such as capacitor mismatch,clock jitter are proposed and simulated. The pipelined ADC system is divided into five parts,clock generator,sample and hold( S/H) circuit,multiplying digital-to-analog converters( MDAC),backend,and digital correction. These blocks introduce several interferences,which attenuate performance of pipelined ADC severely. Modeling and simulations of these disturbance sources are presented particularly. A new model of S/H is introduced. Results derived from simulations can supervise design and optimization of the ADC system.
基金Supported by the National Natural Science Foundation of China(No.61674037)National Major Special Plan of China(No.2018ZX03001008-002)the Double First-Class University and Disciplines Project of China。
文摘A fully integrated wideband voltage-controlled-oscillator(VCO) based on current-reused topology is presented. The overall scheme contains two sub-VCOs, which are controlled by a switch to cover a wide output frequency range. Fabricated in TSMC 65 nm CMOS technology, the measured output frequency of the VCO ranges from 3.991 GHz to 9.713 GHz,achieving a tuning range of 83.5%. And the worst and best phase noise at 1 MHz offset are-93.09 dBc/Hz and-111.97 dBc/Hz, respectively. With a 1.2 V supply voltage, the VCO core consumes a current of 3.7-5.1 mA across the entire frequency range. The chip area is 0.51 mm^2, including the pads. Moreover, the proposed VCO provides a figure-of-merit-with-tuning-range(FOM_T) of-191 dBc/Hz to-197 dBc/Hz.
基金Supported by the National Nature Science Foundation of China(No.61674037)the National Key Research and Development Program(No.2016YFC0800400)the Priority Academic Program Development of Jiangsu Higher Education Institutions
文摘A new method of improving speed of latch-type comparators with preamplifier is presented. It investigates the relationship of current and transistor scales which affect delay time(tp) in latch. It applies a mathematical model to optimize latch design. A figure of merit indicates that ratio Ipmos/Inmos is 0.25 in latch leading to optimal delay time. In order to suppress offset of latch, the cross-coupled loading, adopted in telescope preamplifier, which enhances the gain, is well analyzed and designed. The chip is fabricated in 0.18 μm CMOS technology. The delay time of latch comparator is less than 400 ps @500 MHz. The offset of comparator is estimated through Monte Carlo simulation. And power consumption is only 144 W under 1.8 V power supply. Results of on wafer testing are presented at the end of the paper. The chip occupies an area of 0.66×0.55 mm^2 and drains current of 80 μA.
基金Supported by the National Natural Science Foundation of China(No.61674037)National Key Research and Development Program of China(No.2016YFC0800400)the Priority Academic Program Development of Jiangsu Higher Education Institutions
文摘A fractional frequency divider based on phase switching and negative feedback delta-sigma modulator(NF-DSM) is presented. The phase switching circuit, realized by switching 8 signals generated by a divider-by-4 circuit, is adopted to reduce the frequency division step. The NF-DSM, which can obtain smooth output spectra, is proposed to generate the fractional part of the division ratio, moreover, the integer part of the division ratio is realized by a divider-by-2/3 circuit chain. Fabricated in TSMC 0.18 μm RF CMOS technology, the fractional frequency divider achieves a measured operation frequency from 0.5 GHz to 8 GHz. With a 1.8 V supply voltage, the maximum current consumption of the whole divider is 17.5 mA, and the chip area is 0.58 mm^2, including the pads.
基金Project Supported by the National Science and Technology Major Project of China(No.2009ZX03002-004)
文摘This paper presents a wideband low noise amplifier (LNA) for multi-standard radio applications. The low noise characteristic is achieved by the noise-canceling technique while the bandwidth is enhanced by gate- inductive-peaking technique. High-frequency noise performance is consequently improved by the flattened gain over the entire operating frequency band. Fabricated in 0.18 μm CMOS process, the LNA achieves 2.5 GHz of -3 dB bandwidth and 16 dB of gain. The gain variation is within 4-0.8 dB from 300 MHz to 2.2 GHz. The measured noise figure (NF) and average IIP3 are 3.4 dB and -2 dBm, respectively. The proposed LNA occupies 0.39 mm2 core chip area. Operating at 1.8 V, the LNA drains a current of 11.7 mA.