A new approach to reduce the reverse current of Ge pin photodiodes on Si is presented, in which an i-Si layer is inserted between Ge and top Si layers to reduce the electric field in the Ge layer. Without post- growth...A new approach to reduce the reverse current of Ge pin photodiodes on Si is presented, in which an i-Si layer is inserted between Ge and top Si layers to reduce the electric field in the Ge layer. Without post- growth annealing, the reverse current density is reduced to -10 mA/cm^2 at -1 V, i.e., over one order of magnitude lower than that of the reference photodiode without i-Si layer. However, the responsivity of the photodiodes is not severely compromised. This lowered-reverse-current is explained by band-pinning at the i-Si/i-Ge interface. Barrier lowering mechanism induced by E-field is also discussed. The presented ＂non-thermal＂ approach to reduce reverse current should accelerate electronics-photonics convergence by using Oe on the Si complementary metal oxide semiconductor （CMOS） platform.展开更多
基金supported by the Grant-in-Aid for Creative Scientific Research on Si CMOS Photonics in Japan.The meaeurecl devices were fabricated in the Takeda Sentanchi Facility of the University of Tokyo Japan.
文摘A new approach to reduce the reverse current of Ge pin photodiodes on Si is presented, in which an i-Si layer is inserted between Ge and top Si layers to reduce the electric field in the Ge layer. Without post- growth annealing, the reverse current density is reduced to -10 mA/cm^2 at -1 V, i.e., over one order of magnitude lower than that of the reference photodiode without i-Si layer. However, the responsivity of the photodiodes is not severely compromised. This lowered-reverse-current is explained by band-pinning at the i-Si/i-Ge interface. Barrier lowering mechanism induced by E-field is also discussed. The presented ＂non-thermal＂ approach to reduce reverse current should accelerate electronics-photonics convergence by using Oe on the Si complementary metal oxide semiconductor （CMOS） platform.
