A High Voltage BCD Process Using Thin Epitaxial Technology

A high voltage BCD process using thin epitaxial technology is developed for high voltage applications. Compared to conventional thick expitaxial technology, the thickness of the n-type epitaxial layer is reduced to 9μm,and the diffusion processing time needed for forming junction isolation diffusions is substantially reduced. The isolation diffusions have a smaller lateral extent and occupy less chip area. High voltage double RESURF LD- MOS with a breakdown voltage of up to 900V,as well as low voltage CMOS and BJT,are achieved using this high voltage BCD compatible process. An experimental high voltage half bridge gate drive IC using a coupled level shift structure is also successfully implemented, and the high side floating offset voltage in the half bridge drive IC is 880V. The major features of this process for high voltage applications are also clearly demonstrated.

Design of 256 bit single-poly MTP memory based on BCD process

We propose a single-poly MTP （multi-time programmable） cell consisting of one capacitor and two transistors based on MagnaChip＇s BCD process. The area of a unit cell is 37.743 75μm^2. The proposed single-poly MTP cell is erased and programmed by the FN tunnelling scheme. We design a 256 bit MTP memory for PMICs （power management ICs） using the proposed single-poly MTP cells. For small-area designs, we propose a selection circuit between V10V and VSV, and a WL （word-line） driver by simplifying its logic circuit. We reduce the total layout area by using pumped internal node voltages from a seven-stage cross-coupled charge pump for V10V （=10 V） and V5V （=5 V） without any additional charge pumps. The layout size of the designed 256 bit MTP memory is 618.250 μm × 437.425μm.

Cost-Effective VDMOS and Compatible Process for PDP Scan-Driver IC

A VDMOS integrated in a 170V scan-driver chip of a plasma display panel （PDP） is described,which is based on epitaxial bipolar-CMOS-DMOS （BCD） technology. Some key considerations and parameters of the design are discussed. The thickness of epitaxial layer is 17μm, the area of a single VDMOS structure cell is 324μm^2, and only 18 photoetching steps are needed in the development process. It is also compatible with standard CMOS, bipo- lar,and p-LDMOS devices. The breakdown voltage of VDMOS in the process control module （PCM） is more than 200V. Five kinds of VDMOS modules are integrated in 64 channel PDP scan-driver IC, and on-line system verifica- tion is done on a LG-model-42v6 PDP.

A Double High-Voltage p-LDMOS and Its Compatible Process for PDP Scan-Driver ICs

A high-voltage p-LDMOS（HV-pMOS） with field-oxide as gate dielectric and a RESURF drain drift region to undertake high gate-source voltage and drain-source voltage for the scan driver chip of plasma display panels （PDP） is purposed based on the epitaxial bipolar-CMOS-DMOS （BCD） process. The key considerations and parameters of the design are discussed：the thickness of gate dielectrics is 1mm and the area of the device is 80μm × 80μm. Only 18 photoetching steps are needed in the developed process,which is compatible with standard CMOS, bipolar, and VDMOS devices. The breakdown voltage of the HV-pMOS in the process control module （PCM） is more than 200V. The results are favorable for 170V PDP scan driver chips,which contribute to the competitive cost efficiency.

一种用于DC-DC变换器中的斜坡补偿电路

设计了一种应用于DC-DC变换器中的斜坡补偿电路。提出了一种新的动态斜坡补偿方法,使斜坡补偿电流的斜率随着占空比的增大而增大,在消除了次谐波振荡的同时,也避免了斜坡补偿对DC-DC变换器带载能力的影响。该斜坡补偿电路结构简单,易于实现,已在基于0.5μm双极型CMOS DMOS (BCD)工艺设计的电流模降压型DC-DC变换器中得到了验证。测试结果表明,该DC-DC变换器在不同占空比下可稳定工作,可以满足一般的电源应用需求。设计的DC-DC变换器面积为2.2 mm×2.2 mm,其中斜坡补偿电路面积仅为0.2 mm×0.3 mm。

应用于DC-DC转换器的电流采样电路

设计了一种应用于DC-DC转换器的电流采样电路。提出了一种新型的电感等效直流电阻(DCR)采样方法,利用电感自身的DCR实现电流的采样与限流功能,节省了采样电阻,提高了DC-DC转换器的转换效率。同时电路将传统结构中的电流采样电路与脉冲宽度调制(PWM)比较器进行了合并,使系统结构更加简单。在基于0.35μm双极CMOS DMOS(BCD)工艺设计的DC-DC转换器中进行了验证,测试结果表明该DC-DC转换器输入电源电压为4.5~38 V,输出电压为0.6~12 V,负载电流最大可达5 A,转换效率可达95%,可以满足一般的电源应用需求。设计的DC-DC转换器面积为2.30 mm×2.30 mm,其中电流采样电路部分面积仅为0.30 mm×0.40 mm。

一种应用于DC-DC变换器中的片内电源电路

介绍了一种应用在DC-DC变换器芯片中的片内电源电路。其核心是设计了一种带'浮地'结构的对称型跨导放大器电路,既可显著提高电路的瞬态响应速度,也减少了硬件成本,且电路结构简单、易于实现。此外,设计了一种片外电源检测电路,当存在片外5 V电源时,将其接入DC-DC变换器中作为片内主电源,提高了芯片效率。该片内电源电路已在基于0.5μm双极-CMOS-DMOS (BCD)工艺设计的DC-DC变换器中实现了验证,结果表明,采用该片内电源电路可实现宽输入电源范围、一定负载电流条件下的高精度5 V电源输出。DC-DC变换器芯片面积为2.00 mm×1.20 mm,片内电源模块面积仅为0.60 mm×0.40 mm。