Interfacial and electrical properties of HfAIO/GaSb metal-oxide-semiconductor capacitors with sulfur passivation

Interfacial and electrical properties of HfAlO/GaSb metal-oxide-semiconductor capacitors(MOSCAPs) with sulfur passivation were investigated and the chemical mechanisms of the sulfur passivation process were carefully studied. It was shown that the sulfur passivation treatment could reduce the interface trap density Ditof the HfAlO/GaSb interface by 35% and reduce the equivalent oxide thickness(EOT) from 8 nm to 4 nm. The improved properties are due to the removal of the native oxide layer, as was proven by x-ray photoelectron spectroscopy measurements and high-resolution cross-sectional transmission electron microscopy(HRXTEM) results. It was also found that GaSb-based MOSCAPs with HfAlO gate dielectrics have interfacial properties superior to those using HfO2 or Al2O3 dielectric layers.

Mobility enhancement of strained GaSb p-channel metal-oxide-semiconductor field-effect transistors with biaxial compressive strain

Various biaxial compressive strained GaSb p-channel metal-oxide-semiconductor field-effect transistors （MOSFETs） are experimentally and theoretically investigated, The biaxial compressive strained GaSb MOSFETs show a high peak mobility of 638 cm2/V.s, which is 3.86 times of the extracted mobility of the fabricated GaSb MOSFETs without strain. Meanwhile, first principles calculations show that the hole effective mass of GaSb depends on the biaxial compressive strain. The biaxiai compressive strain brings a remarkable enhancement of the hole mobility caused by a significant reduction in the hole effective mass due to the modulation of the valence bands.

Hot-Carrier Effects on Total Dose Irradiated 65 nm n-Type Metal-Oxide-Semiconductor Field-Effect Transistors

The influence of total dose irradiation on hot-carrier reliability of 65 nm n-type metal-oxide-semiconductor field- effect transistors （nMOSFETs） is investigated. Experimental results show that hot-carrier degradations on ir- radiated narrow channel nMOSFETs are greater than those without irradiation. The reason is attributed to radiation-induced charge trapping in shallow trench isolation （STI）. The electric field in the pinch-off region of the nMOSFET is enhanced by radiation-induced charge trapping in STI, resulting in a more severe hot-carrier effect.

Evaluation of a gate-first process for AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with low ohmic annealing temperature

In this paper, TiN/A1Ox gated A1GaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors （MOS- HFETs） were fabricated for gate-first process evaluation. By employing a low temperature ohmic process, ohmic contact can be obtained by annealing at 600 ℃ with the contact resistance approximately 1.6 Ω.mm. The ohmic annealing process also acts as a post-deposition annealing on the oxide film, resulting in good device performance. Those results demonstrated that the TiN/A1Ox gated MOS-HFETs with low temperature ohmic process can be applied for self-aligned gate AIGaN/GaN MOS-HFETs.

Positive Bias Temperature Instability and Hot Carrier Injection of Back Gate Ultra-thin-body In0.53Ga0.47As-on-Insulator n-Channel Metal-Oxide-Semiconductor Field-Effect Transistor

Ultra-thin-body （UTB） In0.53Ga0.47As-on-insulator （In0.53Ga0.47As-OI） structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nmthick A12 03 as a buried oxide by using the direct wafer bonding method. Back gate n-channel metal-oxidesemiconductor field-effect transistors （nMOSFETs） are fabricated by using these In0.53Ga0.47As-OI structures with excellent electrical characteristics. Positive bias temperature instability （PBTI） and hot carrier injection （HCI） characterizations are performed for the In0.53Ga0.47As-OI nMOSFETs. It is confirmed that the In0.53Ga0.47 As-OI nMOSFETs with a thinner body thickness suffer from more severe degradations under both PBTI and HCr stresses. Moreover, the different evolutions of the threshold voltage and the saturation current of the UTB In0.53Ga0.47As-OI nMOSFETs may be due to the slow border traps.

Capacitance characteristics of metal-oxide-semiconductor capacitors with a single layer of embedded nickel nanoparticles for the application of nonvolatile memory

This paper reports that metal-oxide-semiconductor （MOS） capacitors with a single layer of Ni nanopartictes were successfully fabricated by using electron-beam evaporation and rapid thermal annealing for application to nonvolatile memory. Experimental scanning electron microscopy images showed that Ni nanoparticles of about 5 nm in diameter were clearly embedded in the SiO2 layer on p-type Si （100）. Capacitance-voltage measurements of the MOS capacitor show large flat-band voltage shifts of 1.8 V, which indicate the presence of charge storage in the nickel nanoparticles. In addition, the charge-retention characteristics of MOS capacitors with Ni nanoparticles were investigated by using capacitance-time measurements. The results showed that there was a decay of the capacitance embedded with Ni nanoparticles for an electron charge after 104 s. But only a slight decay of the capacitance originating from hole charging was observed. The present results indicate that this technique is promising for the efficient formation or insertion of metal nanoparticles inside MOS structures.

X-ray detection based on complementary metal-oxide-semiconductor sensors

Complementary metal-oxide-semiconductor(CMOS) sensors can convert X-rays into detectable signals; therefore, they are powerful tools in X-ray detection applications. Herein, we explore the physics behind X-ray detection performed using CMOS sensors. X-ray measurements were obtained using a simulated positioner based on a CMOS sensor, while the X-ray energy was modified by changing the voltage, current, and radiation time. A monitoring control unit collected video data of the detected X-rays. The video images were framed and filtered to detect the effective pixel points(radiation spots).The histograms of the images prove there is a linear relationship between the pixel points and X-ray energy. The relationships between the image pixel points, voltage, and current were quantified, and the resultant correlations were observed to obey some physical laws.

Influences of fringing capacitance on threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor

Models of threshold voltage and subthreshold swing, including the fringing-capacitance effects between the gate electrode and the surface of the source/drain region, are proposed. The validity of the proposed models is confirmed by the good agreement between the simulated results and the experimental data. Based on the models, some factors impacting the threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor（MOSFET） are discussed in detail and it is found that there is an optimum thickness of gate oxide for definite dielectric constant of gate oxide to obtain the minimum subthreshold swing. As a result, it is shown that the fringing-capacitance effect of a shortchannel GeOI MOSFET cannot be ignored in calculating the threshold voltage and subthreshold swing.

GaSb p-channel metal-oxide-semiconductor field-effect transistor and its temperature dependent characteristics

GaSb p-channel metal-oxide-semiconductor field-effect transistors （MOSFETs） with an atomic layer deposited Al2O3 gate dielectric and a self-aligned Si-implanted source/drain are experimentally demonstrated. Temperature dependent electrical characteristics are investigated. Different electrical behaviors are observed in two temperature regions, and the un- derlying mechanisms are discussed. It is found that the reverse-bias pn junction leakage of the drain/substrate is the main component of the off-state drain leakage current, which is generation-current dominated in the low temperature regions and is diffusion-current dominated in the high temperature regions. Methods to further reduce the off-state drain leakage current are given.

The study on mechanism and model of negative bias temperature instability degradation in P-channel metal-oxide-semiconductor field-effect transistors

Negative Bias Temperature Instability （NBTI） has become one of the most serious reliability problems of metaloxide-semiconductor field-effect transistors （MOSFETs）. The degradation mechanism and model of NBTI are studied in this paper. From the experimental results, the exponential value 0.25-0.5 which represents the relation of NBTI degradation and stress time is obtained. Based on the experimental results and existing model, the reaction-diffusion model with H^＋ related species generated is deduced, and the exponent 0.5 is obtained. The results suggest that there should be H^＋ generated in the NBTI degradation. With the real time method, the degradation with an exponent 0.5 appears clearly in drain current shift during the first seconds of stress and then verifies that H^＋ generated during NBTI stress.

Performance of La203/InA1N/GaN metal-oxide-semiconductor high electron mobility transistors

We report on the performance of La203/InA1N/GaN metal-oxide-semiconductor high electron mobility transistors （MOSHEMTs） and InA1N/GaN high electron mobility transistors （HEMTs）. The MOSHEMT presents a maximum drain current of 961 mA/mm at Vgs = 4 V and a maximum transconductance of 130 mS/mm compared with 710 mA/mm at Vgs = 1 V and 131 mS/mm for the HEMT device, while the gate leakage current in the reverse direction could be reduced by four orders of magnitude. Compared with the HEMT device of a similar geometry, MOSHEMT presents a large gate voltage swing and negligible current collapse.

Fabrication and Characterization of 1700 V 4H-SiC Vertical Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors

The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors （VDMOSFETs） are reported. The drift layer is 17μm in thickness with 5 × 10^15 cm^-3 n-type doping, and the channel length is 1μm. The MOSFETs show a peak mobility of 17cm2/V.s and a typical threshold voltage of 3 V. The active area of 0.028cm2 delivers a forward drain current of 7A at Vcs = 22 V and VDS= 15 V. The specific on-resistance （Ron,sv） is 18mΩ.cm2 at VGS= 22 V and the blocking voltage is 1975 V （IDS 〈 lOOnA） at VGS = 0 V.

Interfacial and Electrical Properties of GaAs Metal-Oxide-Semiconductor Capacitor with ZrAlON as the Interfacial Passivation Layer

The ZrTiON gate-dielectric GaAs metal-oxide-semiconductor （MOS） capacitors with or without ZrAION as the interfacial passivation layer （IPL） are fabricated and their properties are investigated. The experimental results show that the GaAs MOS capacitor with the ZrAION IPL exhibits better interracial and electrical properties, including lower interface-state density （1.14 × 10^12 cm^-2eV^-1）, smaller gate leakage current （6.82 × 10^-5 A//cm^2 at Vfb ＋1V）, smaller capacitance equivalent thickness （1.5 nm）, and larger k value （26）. The involved mechanisms lie in the fact that the ZrAION IPL can effectively block the diffusion of Ti and O towards the GaAs surface, thus suppressing the formation of interracial Ga-/As-oxides and As-As dimers, which leads to improved interracial and electrical properties for the devices.

Experimental I-V and C-V Analysis of Schottky-Barrier Metal-Oxide-Semiconductor Field Effect Transistors with Epitaxial NiSi2 Contacts and Dopant Segregation

We present an experimental analysis of Schottky-barrier metal-oxide-semiconductor field effect transistors （SB- MOSFETs） fabricated on ultrathin body silicon-on-insulator substrates with a steep junction by the dopant implantation into the silicide process. The subthreshold swing of such SB-MOSFETs reaches 69mV/dec. Em- phasis is placed on the capacitance-voltage analysis of p-type SB-MOSFETs. According to the measurements of gate-to-source capacitance Cgs with respect to Vgs at various Vds, we find that a maximum occurs at the accumulation regime due to the most imbalanced charge distribution along the channel. At each Cgs peak, the difference between Vgs and Vds is equal to the Schottky barrier height （SBH） for NiSi2 on highly doped silicon, which indicates that the critical condition of channel pinching off is related with SBH for source/drain on chan- nel. The SBH for NiSi2 on highly doped silicon can affect the pinch-off voltage and the saturation current of SB-MOSFETs.

Low working loss Si/4H-SiC heterojunction MOSFET with analysis of the gate-controlled tunneling effect

A silicon (Si)/silicon carbide (4H-SiC) heterojunction double-trench metal-oxide-semiconductor field effect transistor (MOSFET) (HDT-MOS) with the gate-controlled tunneling effect is proposed for the first time based on simulations. In this structure, the channel regions are made of Si to take advantage of its high channel mobility and carrier density. The voltage-withstanding region is made of 4H-SiC so that HDT-MOS has a high breakdown voltage (BV) similar to pure 4H-SiC double-trench MOSFETs (DT-MOSs). The gate-controlled tunneling effect indicates that the gate voltage (V_(G)) has a remarkable influence on the tunneling current of the heterojunction. The accumulation layer formed with positive VG can reduce the width of the Si/SiC heterointerface barrier, similar to the heavily doped region in an Ohmic contact. This narrower barrier is easier for electrons to tunnel through, resulting in a lower heterointerface resistance. Thus, with similar BV (approximately 1770 V), the specific on-state resistance (R_(ON-SP)) of HDT-MOS is reduced by 0.77 mΩ·cm^(2) compared with that of DT-MOS. The gate-to-drain charge (Q_(GD)) and switching loss of HDT-MOS are 52.14% and 22.59% lower than those of DT-MOS, respectively, due to the lower gate platform voltage (V_(GP)) and the corresponding smaller variation (ΔV_(GP)). The figure of merit (Q_(GD)×R_(ON-SP)) of HDT-MOS decreases by 61.25%. Moreover, the heterointerface charges can reduce RON-SP of HDT-MOS due to trap-assisted tunneling while the heterointerface traps show the opposite effect. Therefore, the HDT-MOS structure can significantly reduce the working loss of SiC MOSFET, leading to a lower temperature rise when the devices are applied in the system.

A High-Performance Silicon Electro-Optic Phase Modulator with a Triple MOS Capacitor

We propose and analyze a novel Si-based electro-optic modulator with an improved metal-oxide-semiconductor （MOS） capacitor configuration integrated into silicon-on-insulator （SOl）. Three gate-oxide layers embedded in the silicon waveguide constitute a triple MOS capacitor structure, which boosts the modulation efficiency compared with a single MOS capacitor. The simulation results demonstrate that the Vπ Lπ product is 2. 4V · cm. The rise time and fall time of the proposed device are calculated to be 80 and 40ps from the transient response curve, respectively,indicating a bandwidth of 8GHz. The phase shift efficiency and bandwidth can be enhanced by rib width scaling.

Neuronal signal detecting and stimulating circuit array for monolithic integrated MEA

A neuronal signal detecting circuit and a neuronal signal stimulating circuit designed for a monolithic integrated MEA（micro-electrode array） system are described. As a basic cell of the circuits, an OPA（ operational amplifier） is designed with low power, low noise, small size and high gain. The detecting circuit has a chip area of 290 μm × 400 μm, a power dissipation of 2.02 mW, an equivalent input noise of 17.72 nV/ Hz, a gain of 60. 5 dB, and an output voltage from - 2. 48 to ＋ 2. 5 V. The stimulating circuit has a chip area of 130 μm × 290 μm, a power dissipation of 740 μW, and an output voltage from - 2. 5 to 2. 04 V. The parameters show that two circuits are suitable for a monolithic integrated MEA system. The detecting circuit and MEA have been fabricated. The test results show that the detecting circuit works well.

SPICE model of trench-gate MOSFET device

A novel simulation program with an integrated circuit emphasis（SPICE） model developed for trench-gate metal-oxide-semiconductor field-effect transistor（M OSFET）devices is proposed. The drift region resistance was modeled according to the physical characteristics and the specific structure of the trench-gate MOSFET device. For the accurate simulation of dynamic characteristics, three important capacitances, gate-to-drain capacitance Cgd, gate-to-source capacitance Cgsand drain-to-source capacitance Cds, were modeled, respectively, in the proposed model. Furthermore,the self-heating effect, temperature effect and breakdown characteristic were taken into account; the self-heating model and breakdown model were built in the proposed model; and the temperature parameters of the model were revised. The proposed model is verified by experimental results, and the errors between measured data and simulation results of the novel model are less than 5%. Therefore, the model can give an accurate description for both the static and dynamic characteristics of the trench-gate MOSFET device.

基于LSTM-DHMM的MOSFET器件健康状态识别与故障时间预测

针对MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)器件故障预测与健康管理问题,提出了一种长短时记忆(Long Short-Term Memory,LSTM)算法与离散隐马尔可夫模型(Discrete Hidden Markov Model,DHMM)相结合的故障预测新方法.该方法利用LSTM算法预测器件状态发展趋势;用自回归(AutoRegressive,AR)模型提取故障信息特征;以DHMM建立特征向量和退化等级之间的映射关系;在LSTM-DHMM模型预测结果的基础上,结合失效阈值排除虚警并预测故障时间,预测误差小于10%,精度较高.与GRU-DHMM(Gated Recurrent Unit Discrete Hidden Markov Model)、GRU-SVM(Gated Recurrent Unit Support Vector Machine)、LSTM-SVM(Long Short-Term Memory Support Vector Machine)方法进行对比分析,结果表明,LSTM-DHMM的预测准确率高于其他三种方案,能有效识别实验器件健康状态、较好预测故障时间,具有有效性和优越性.

碳化硅MOSFET栅氧化层可靠性研究

通过TCAD仿真的方法对器件可靠性与结构设计之间的关系进行分析;对栅极电压和栅氧化层最强电场进行仿真,以对碳化硅金属氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor,MOSFET)单胞结构参数进行优化;在N型碳化硅外延层上制作金属氧化物半导体(metal-oxide-semiconductor,MOS)电容,并且通过对MOS电容进行C-V测试的方法评估Si O2/Si C界面质量。对导带附近界面陷阱密度进行比较。NO退火的样品与干氧氧化样品相比界面质量明显改善,界面态密度小于5×10~11 cm–2e V–1。