To achieve high parallel computation of discrete wavelet transform （DWT） in JPEG2000, a high-throughput two-dimensional （2D） 9/7 DWT very large scale integration （VLSI） design is proposed, in which the row proce...To achieve high parallel computation of discrete wavelet transform （DWT） in JPEG2000, a high-throughput two-dimensional （2D） 9/7 DWT very large scale integration （VLSI） design is proposed, in which the row processor is based on flipping structure. Due to the difference of the input data flow, the column processor is obtained by adding the input selector and data buffer to the row processor. Normalization steps in row and column DWT are combined to reduce the number of multipliers, and the rationality is verified. By rearranging the output of four-line row DWT with a multiplexer （MUX）, the amount of data processed by each column processor becomes half, and the four-input/four- output architecture is implemented. For an image with the size of N x N, the computing time of one-level 2D 9/7 DWT is 0.25N2 ＋ 1.5N clock cycles. The critical path delay is one multiplier delay, and only 5N internal memory is required. The results of post-route simulation on FPGA show that clock frequency reaches 136 MHz, and the throughput is 544 Msample/s, which satisfies the requirements of high-speed applications.展开更多
In order to develop the core chip supporting binocular stereo displays for head mounted display （HMD） and glasses-TV, a very large scale integrated （VISI） design scheme is proposed by using a pipeline architecture...In order to develop the core chip supporting binocular stereo displays for head mounted display （HMD） and glasses-TV, a very large scale integrated （VISI） design scheme is proposed by using a pipeline architecture for 3D display processing chip （HMD100）. Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation, and their hardware implementations which improve the image quality are presented. The proposed HMD100 chip is verified by the field-programmable gate array （FPGA）. As one of innovative and high integration SoC chips, HMD100 is designed by a digital and analog mixed circuit. It can support binocular stereo display, has better scaling effect and integration. Hence it is applicable in virtual reality （VR）, 3D games and other microdisplay domains.展开更多
为提高Exp-Golomb码的编解码效率,提出了一种基于快速"首位1检测"的Exp-Golomb编解码器硬件实现方法,降低了计算量并节省了硬件资源。该Exp-Golomb编解码器已通过RTL(Register Transfer Level)级仿真和综合,并在FPGA(Field Pr...为提高Exp-Golomb码的编解码效率,提出了一种基于快速"首位1检测"的Exp-Golomb编解码器硬件实现方法,降低了计算量并节省了硬件资源。该Exp-Golomb编解码器已通过RTL(Register Transfer Level)级仿真和综合,并在FPGA(Field Programmable Gate Array)开发平台进行了验证,在133 MHz时钟频率下编解码器的综合门数分别为765门和632门。该编解码器能满足Baseline档次(30帧/s),分辨率为352×288视频序列的实时编解码对质量和速度的要求。展开更多
基金The National Science and Technology M ajor Project of the M inistry of Science and Technology of China(No.2014ZX03003007-009)
文摘To achieve high parallel computation of discrete wavelet transform （DWT） in JPEG2000, a high-throughput two-dimensional （2D） 9/7 DWT very large scale integration （VLSI） design is proposed, in which the row processor is based on flipping structure. Due to the difference of the input data flow, the column processor is obtained by adding the input selector and data buffer to the row processor. Normalization steps in row and column DWT are combined to reduce the number of multipliers, and the rationality is verified. By rearranging the output of four-line row DWT with a multiplexer （MUX）, the amount of data processed by each column processor becomes half, and the four-input/four- output architecture is implemented. For an image with the size of N x N, the computing time of one-level 2D 9/7 DWT is 0.25N2 ＋ 1.5N clock cycles. The critical path delay is one multiplier delay, and only 5N internal memory is required. The results of post-route simulation on FPGA show that clock frequency reaches 136 MHz, and the throughput is 544 Msample/s, which satisfies the requirements of high-speed applications.
文摘In order to develop the core chip supporting binocular stereo displays for head mounted display （HMD） and glasses-TV, a very large scale integrated （VISI） design scheme is proposed by using a pipeline architecture for 3D display processing chip （HMD100）. Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation, and their hardware implementations which improve the image quality are presented. The proposed HMD100 chip is verified by the field-programmable gate array （FPGA）. As one of innovative and high integration SoC chips, HMD100 is designed by a digital and analog mixed circuit. It can support binocular stereo display, has better scaling effect and integration. Hence it is applicable in virtual reality （VR）, 3D games and other microdisplay domains.
