Neutron irradiation influence on high-power thyristor device under fusion environment

Because of their economy and applicability,high-power thyristor devices are widely used in the power supply systems for large fusion devices.When high-dose neutrons produced by deuterium–tritium(D–T)fusion reactions are irradiated on a thyristor device for a long time,the electrical characteristics of the device change,which may eventually cause irreversible damage.In this study,with the thyristor switch of the commutation circuit in the quench protection system(QPS)of a fusion device as the study object,the relationship between the internal physical structure and external electrical parameters of the irradiated thyristor is established.Subsequently,a series of targeted thyristor physical simulations and neutron irradiation experiments are conducted to verify the accuracy of the theoretical analysis.In addition,the effect of irradiated thyristor electrical characteristic changes on the entire QPS is studied by accurate simulation,providing valuable guidelines for the maintenance and renovation of the QPS.

100 kA/10kV thyristor stack design for the quench protection system in CRAFT

Thyristors have longer lifetimes,higher reliability,and very high voltage and current ratings and they require less maintenance than other high-power semiconductor devices.As a result,they are particularly suitable for quench protection systems(QPSs),which protect the superconducting magnets in large fusion devices from damage.In this paper,we propose a design for a 100 k A/10 k V thyristor stack supported by both theoretical and simulation-based analyses as well as experimental verification.Due to the ultrahigh electrical performance requirements imposed on the QPS by the Comprehensive Research Facility for Fusion Technology(CRAFT),three main issues must be considered:the voltage-balancing problem caused by multiple thyristors in a series structure,the increased junction temperature problem caused by extremely high currents,and the reverse recovery phenomenon that arises from the thyristor’s physical structure.Hence,a series of detailed theoretical analyses,simulations,and experiments,including a thyristor junction temperature prediction method and reverse recovery process modeling,were carried out to optimize the design.Finally,the reliability and stability of the thyristor stack were verified by a series of prototype experiments.The results confirmed the correctness and accuracy of the proposed thyristor stack design method and also indicated that the proposed thyristor stack can meet the application conditions of a 100 k A QPS in the CRAFT project.

Improvement of circuit oscillation generated by underwater high voltage pulse discharges based on pulse power thyristor

High voltage fracturing technology was widely used in the field of reservoir reconstruction due to its advantages of being clean, pollution-free, and high-efficiency. However, high-frequency circuit oscillation occurs during the underwater high voltage pulse discharge process, which brings security risks to the stability of the pulse fracturing system. In order to solve this problem, an underwater pulse power discharge system was established, the circuit oscillation generation conditions were analyzed and the circuit oscillation suppression method was proposed. Firstly, the system structure was introduced and the charging model of the energy storage capacitor was established by the state space average method. Next, the electrode high-voltage breakdown model was established through COMSOL software, the electrode breakdown process was analyzed according to the electron density distribution image, and the plasma channel impedance was estimated based on the conductivity simulation results. Then the underwater pulse power discharge process and the circuit oscillation generation condition were analyzed, and the circuit oscillation suppression strategy of using the thyristor to replace the gas spark switch was proposed. Finally, laboratory experiments were carried out to verify the precision of the theoretical model and the suppression effect of circuit oscillation. The experimental results show that the voltage variation of the energy storage capacitor, the impedance change of the pulse power discharge process, and the equivalent circuit in each discharge stage were consistent with the theoretical model. The proposed oscillation suppression strategy cannot only prevent the damage caused by circuit oscillation but also reduce the damping oscillation time by77.1%, which can greatly improve the stability of the system. This research has potential application value in the field of underwater pulse power discharge for reservoir reconstruction.

Analysis and Optimization of the Characteristics of a New IEC-GTO Thyristor

Based on a short anode GTO structure （SA-GTO）,a novel GTO structure called an injection efficiency controlled gate turn off thyristor （IEC-GTO） is proposed,in which the injection efficiency can be controlled via an additional thin oxide layer located in the short anode contact region. The forward blocking, conducting, and switching characteristics are analyzed and compared with an SA-GTO and conventional GTO. The results show that the IEC-GTO can obtain a better trade-off relation between on-state and turn-off characteristics. Additionally,the width of the oxide layer covering the anode region and the doping concentration of the anode region are optimized, the process feasibility is analyzed, and a realization scheme is given. The results show that the introduction of an oxide layer would not increase the complexity of process of the IEC-GTO.

Trench MOS Controlled Thyristor

A new structure of power MOS-gated thyristor named Trench MOS Controlled Thyristor (TMCT) is presented.The MOSFETs used to turn on and turn off the thrysitor are formed with UMOS technology.No parasitic transistors exist in this structure,so the problems created by the parasitic transistors can be eliminated.So,the TMCT is expected to be of better performance.The experimental results of the multicellular 600V TMCT with the active area of 02mm2 show that the on-state drop is 125V at 300A/cm2,and the maximum controllable current reaches 296A/cm2 at the gate voltage of -20V and with an inductive load.

Injection modulation of p^+-n emitter junction in 4H-SiC light triggered thyristor by double-deck thin n-base

To overcome hole-injection limitation of p^＋-n emitter junction in 4H-SiC light triggered thyristor, a novel high- voltage 4H-SiC light triggered thyristor with double-deck thin n-base structure is proposed and demonstrated by two- dimensional numerical simulations. In this new structure, the conventional thin n-base is split to double-deck. The hole- injection of p^＋-n emitter junction is modulated by modulating the doping concentration and thickness of upper-deck thin n- base. With double-deck thin n-base, the current gain coefficient of the top pnp transistor in 4H-SiC light triggered thyristor is enhanced. As a result, the triggering light intensity and the turn-on delay time of 4H-SiC light triggered thyristor are both reduced. The simulation results show that the proposed 10-kV 4H-SiC light triggered thyristor is able to be triggered on by 500-mW/cm^2 ultraviolet light pulse. Meanwhile, the turn-on delay time of the proposed thyristor is reduced to 337 ns.

Shortening turn-on delay of SiC light triggered thyristor by7-shaped thin n-base doping profile

A new 4 H–SiC light triggered thyristor（LTT） with 7-shaped thin n-base doping profile is proposed and simulated using a two-dimensional numerical method. In this new structure, the bottom region of the thin n-base has a graded doping profile to induce an accelerating electric field and compensate for the shortcoming of the double-layer thin n-base structure in transmitting injected holes. In addition, the accelerating electric field can also speed up the transmission of photongenerated carriers during light triggering. As a result, the current gain of the top pnp transistor of the SiC LTT is further increased. According to the TCAD simulations, the turn-on delay time of the SiC LTT decreases by about 91.5% compared with that of previous double-layer thin n-base SiC LTT. The minimum turn-on delay time of the SiC LTT is only 828 ns,when triggered by 100 mW/cm^2 ultraviolet light. Meanwhile, there is only a slight degradation in the forward blocking characteristic.

General Consideration of Measuring System for Operational Test of Thyristor Valves of Ultra High Voltage DC Power Transmission

Thyristor valve is one of the key equipments for ultra high voltage direct current(UHVDC) power transmission projects.Before being installed on site,they need to be tested in a laboratory in order to verify their operational performance to satisfy the technical specification of project related.Test facilities for operational tests of thyristor valves are supposed to enable to undertake more severe electrical stresses than those being applied in the thyristor valves under test(test objects).On the other hand,the stresses applied into the test objects are neither higher nor lower than specified by the specification,because inappropriate stresses applied would result in incorrect evaluation of performance on the test objects,more seriously,would cuase the damage of test objects with expensive cost losing.Generally,the process of operational tests is complicated and performed in a complex synthetic test circuit(hereafter as STC),where there are a lot of sensors used for measuring,monitoring and protection on line to ensure that the test circuit functions in good condition.Therefore,the measuring systems embedded play a core role in STC,acting like "eyes".Based on the first project of building up a STC in China,experience of planning measuring systems is summarized so as to be referenced by related engineers.

Ultra-high voltage 4H-SiC gate turn-off thyristor for low switching time

An ultra-high voltage 4H-silicon carbide(Si C) gate turn-off(GTO) thyristor for low switching time is proposed and analyzed by numerical simulation. It features a double epitaxial p-base in which an extra electrical field is induced to enhance the transportation of the electrons in the thin p-base and reduce recombination. As a result, the turn-on characteristics are improved. What is more, to obtain a low turn-off loss, an alternating p^+/n^+region formed in the backside acts as the anode in the GTO thyristor. Consequently, another path formed by the reverse-biased n^+–p junction accelerates the fast removal of excess electrons during turn-off. This work demonstrates that the turn-on time and turn-off time of the new structure are reduced to 37 ns and 783.1 ns, respectively, under a bus voltage of 8000 V and load current of 100 A/cm^2.

High dV/dt immunity MOS controlled thyristor using a double variable lateral doping technique for capacitor discharge applications

An analysis model of the dV/dt capability for a metal-oxide-semiconductor （MOS） controlled thyristor （MCT） is developed. It is shown that, in addition to the P-well resistance reported previously, the existence of the OFF-FET channel resistance in the MCT may degrade the dV/dt capability. Lower P-well and N-well dosages in the MCT are useful in getting a lower threshold voltage of OFF-FET and then a higher dV/dt immunity. However, both dosages are restricted by the requirements for the blocking property and the forward conduction capability. Thus, a double variable lateral doping （DVLD） technique is proposed to realize a high dV/dt immunity without any sacrifice in other properties. The accuracy of the developed model is verified by comparing the obtained results with those from simulations. In addition, this DVLD MCT features mask-saving compared with the conventional MCT fabrication process. The excellent device performance, coupled with the simple fabrication, makes the proposed DVLP MCT a promising candidate for capacitor discharge applications.

A Comparison Study of Input ESD Protection Schemes Utilizing NMOS, Thyristor, and Diode Devices

For three fundamental input-protection schemes suitable for high-frequency CMOS ICs, which utilize protection devices such as NMOS transistors, thyristors, and diodes, we attempt an in-depth comparison on HBM ESD robustness in terms of lattice heating inside protection devices and peak voltages developed across gate oxides in input buffers, based on DC, mixed-mode transient, and AC analyses utilizing a 2-dimensional device simulator. For this purpose, we construct an equivalent circuit model of input HBM test environments for CMOS chips equipped with input ESD protection circuits, which allows mixed-mode transient simulations for various HBM test modes. By executing mixed-mode simulations including up to six active protection devices in a circuit, we attempt a detailed analysis on the problems, which can occur in real tests. In the procedure, we suggest to a recipe to ease the bipolar trigger in the protection devices and figure out that oxide failure in internal circuits is determined by the peak voltage developed in the later stage of discharge, which corresponds to the junction breakdown voltage of the NMOS structure residing in the protection devices. We explain strength and weakness of each protection scheme as an input ESD protection circuit for high-frequency ICs, and suggest valuable guidelines relating design of the protection devices and circuits.

Investigation into Equivalency of Synthetic Test Circuit Used for Operational Tests of Thyristor Valves for UHVDC

With the growth of capacity of high voltage direct current(HVDC) transmission lines,the ratings of thyristor valves,which are one of the most critical equipments,are getting higher and higher.Verification of performance of thyristor valves particularly designed for HVDC project plays an important role in the handover of products between the manufacturer and the client.Conventional test facilities based on philosophy of direct test cannot meet the requirements for modern thyristor valves.New test facilities with high ratings are necessarily built based on philosophy of synthetic test.Over the conventional direct test circuit,the later is an economical and feasible solution with less financial investment and higher test capability.However,the equivalency between the synthetic test and the direct test should be analyzed technically in order to make sure that the condition of verification test in a synthetic test circuit should satisfy the actual operation condition of thyristor valves existing in a real HVDC project,just as in a direct test circuit.Equivalency analysis is focused in this paper,covering the scope of thyristor valves' steady state,and transient state.On the basis of the results achieved,a synthetic test circuit of 6 500 A/50 kV for operational tests of thyristor valves used for up to UHVDC project has newly been set up and already put into service in Xi'an High Voltage Apparatus Research Institute Co.,Ltd.(XIHARI),China.Some of the results have been adopted also by a new national standard of China.

Research on Reverse Recovery Transient of Parallel Thyristors for Fusion Power Supply

In nuclear fusion power supply systems, the thyristors often need to be connected in parallel for sustaining large current. However, research on the reverse recovery transient of parallel thyristors has not been reported yet. When several thyristors are connected in parallel,they cannot turn-off at the same moment, and thus the turn-off model based on a single thyristor is no longer suitable. In this paper, an analysis is presented for the reverse recovery transient of parallel thyristors. Parallel thyristors can be assumed as one virtual thyristor so that the reverse recovery current can be modeled by an exponential function. Through equivalent transformation of the rectifier circuit, the commutating over-voltage can be calculated based on Kirchhoff’s equation. The reverse recovery current and commutation over-voltage waveforms are measured on an experiment platform for a high power rectifier supply. From the measurement results, it is concluded that the modeling method is acceptable.

Hybrid Operation of Fault Current Limiter and Thyristor Controlled Braking Resistor

The effectiveness of a combination of fault current limiter and thyristor controlled braking resistor on power system stability enhancement and damping turbine shaft torsional oscillations has been studied. If both devices operate at the same bus, the stabilization control scheme can be carried out continuously and with flexibility. As a result, the fault currents are limited, and the generator disturbances and the turbine shaft torsional oscillations are converged quickly. In this paper, the effectiveness of the combination of both devices has been demonstrated by considering 3LG （three-lines-to-ground） fault in a two-machine infinite bus system. Also, temperature rise effect of both devices with various resistance values and weights has been demonstrated. Simulation results indicate a significant power system stability enhancement and damping turbine shaft torsional oscillations as well as with allowable temperature rise.

High current pulse forming network switched by static induction thyristor

A high-current pulse forming network (PFN) has been developed for applications to artificial solar-wind generation. It is switched by staticinduction thyristor (SIThy) and is capable of generating pulsed current of ~9.7 kA for a time duration of ~1 ms. The SIThy switch module ismade that it can be controlled by an optical signal and it can be operated at elevated electrical potential. The experiments reported in this paperused two switch modules connected in series for maximum operating voltage of 3.5 kV. The experimental results have demonstrated a pulsedhigh-current generator switched by semiconductor devices, as well as the control and operation of SIThy for pulsed power application.

Study on Heat Dissipater for High-Power Thyristors in Explosion-Proof Shell

A new type water-cooled heat dissipater for multiple high-power thyristors in explosion-proof shell used in coal mine was designed, and then, the numerical computation of the three-dimensional steady-state temperature distributions under different working conditions for cooling core was conducted in order to understand in detail the heat transfer performance. Based on the computation results, the temperature differences and the maximum heat transfer rates were given. These results of the study on the heat dissipater lay a basis for optimising its structure design and guiding its operation.

A STUDY ON HEAT PIPE RADIATOR USED FOR THE COOLING OF THE HIGH-POWER THYRISTOR IN EXPLOSION-PROOF SHELL

The cooling of the high-power thyristor (HPT) in explosion-proof sbcll (EPS) used inmining pit has been a difficult problem for a long time. It has some spectal demands. According toheat pipe’s working principle, this paper introduced a kind of newly devcloped beat pipe radiatorSeveral HPT in EPS can be cooled by one beat pipe. In order to obtain the cooling and forced convection cooling , two dimensionless equations were obtained. This paper also studicd the refation between the surface temperature of HPT and the working electric current. The corresponding curvewas given out. Experiments shown that the beat pipe radistor introdued in this paper could effectively cool the HPT in EPS. It becomes a practical and valuable new technique.

A Thyristor-Only Input ESD Protection Scheme for CMOS RF ICs

We propose an input protection scheme composed of thyristor devices only without using a clamp NMOS device in order to minimize the area consumed by a pad structure in CMOS RF ICs. For this purpose, we suggest low-voltage triggering thyristor protection device structures assuming usage of standard CMOS processes, and attempt an in-depth comparison study with a conventional thyristor protection scheme incorporating a clamp NMOS device. The comparison study mainly focuses on robustness against the HBM ESD in terms of peak voltages applied to gate oxides in an input buffer and lattice heating inside protection devices based on DC and mixed-mode transient analyses utilizing a 2-dimensional device simulator. We constructed an equivalent circuit for the input HBM test environment of the CMOS chip equipped with the input ESD protection devices. And by executing mixed-mode simulations including up to four protection devices and analyzing the results for five different test modes, we attempt a detailed analysis on the problems which can occur in real HBM tests. We figure out strength of the proposed thyristor-only protection scheme, and suggest guidelines relating the design of the protection devices and circuits.

A Study of High-Power Thyristor Switch of Poloidal-Field Power Supply System in HT-7U Super-Conductive Tokamak

Through theoretical analysis of thyristor switch, criterion of turn-off was derived for the design of thyristor switch. The expression of parameter design and its math model during the turn-off were deduced. The simulation and experiment have been accomplished to validate the analysis.

Direct on Line Starting Induction Motor with Thyristor Switched Capacitor Based Voltage Regulation

The purpose of this paper is to show a laboratory scale implementation of a Thyristor Switched Capacitors （TSC） as an alternative for voltage regulation during a direct on line three-phase induction motor starting on an emulated weak transmission line. Thyristor switched capacitor bank was chosen because it is a well known topology, considering the very nature of the direct starting induction motors, which represents a highly inductive load, the use of switched reactors becomes unnecessary. Such fact minimizes the introduction of harmonics components, and also reduces the cost of the implementation. The binary disposition of the banks allows a variable Var compensation with sixteen steps, in this case. The solution makes use of low cost devices combined with sliding window voltage and current measurement algorithm and a PI control with dead band control for achieve the shown experimental results, where the system is able to manage a typically 20% voltage drop, reducing it to less than 4%. The schematic of the developed circuit, the control technique and a quite simple method to calculate the binary weight capacitors banks are also presented.