Dual-Delay-Path Ring Oscillator with Self-Biased Delay Cells for Clock Generation

This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply VDD = 1.8 V, the resulting set of performance parameters include power consumption PDC = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving PDC and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.

Delay-Based User Association in Heterogeneous Networks with Backhaul

The Internet of things(IoT) as an important application of future communication networks puts a high premium on delay issues. Thus when Io T applications meet heterogeneous networks(HetNets) where macro cells are overlaid with small cells, some traditional problems need rethinking. In this paper, we investigate the delay-addressed association problem in two-tier Het Nets considering different backhaul technologies. Specifically, millimeter wave and fiber links are used to provide high-capacity backhaul for small cells. We first formulate the user association problem to minimize the total delay which depends on the probability of successful transmission, the number of user terminals(UTs), and the number of base stations(BSs). And then two algorithms for active mode and mixed mode are proposed to minimize the network delay. Simulation results show that algorithms based on mutual selection between UTs and BSs have better performance than those based on distance. And algorithms for mixed modes have less delay than those for active mode when the number of BSs is large enough, compared to the number of UTs.

A low-power DCO using inverter interlaced cascaded delay cell

This paper presents a low-power small-area digitally controlled oscillator （DCO） using an inverters interlaced cascaded delay cell （IICDC）. It uses a coarse-fine architecture with binary-weighted delay stages for the delay range and resolution. The coarse-tuning stage of the DCO uses IICDC, which is power and area efficient with low phase noise, as compared with conventional delay cells. The ADPLL with a DCO is fabricated in the UMC 180-nm CMOS process with an active area of 0.071 mm2. The output frequency range is 140-600 MHz at the power supply of 1.8 V. The power consumption is 2.34 mW@ a 200 MHz output.

STABILITY ANALYSIS OF A DISCRETE NONLINEAR DELAY SURVIVAL RED BLOOD CELLS MODEL

In this article we consider the kth-order discrete delay survival red blood cells model. The general form of the discrete dynamical system is rewritten as Xn＋l = f（Pn,δn,xn,... ,xn＋1） where Pn,δn converge to the parametric values P and 6. We show that when the parameters are replaced by sequences, the stability results of the original system still hold.

Monoclonal anti-idiotype antibody bearing the internal image of nasopharyngeal carcinoma associated antigen

Objective To generate and characterize anti-idiotypic monoclonal antibody (Ab2) that bears the internal image of nasopharyngeal carcinoma (NPC) associated antigen. Methods Using NPC monoclonal antibody (Ab1) as immunogen, hybridoma cells were obtained by fusion of SP2/0 myeloma cells with immunized murine spleen cells. Positive clones were screened by Sandwich ELISA and a binding inhibition test. To determine whether Ab2 possess the internal image of the original antigen or not, mice were immunized with Ab2. ELISA and the competitive inhibition assay tested anti-anti-idiotypic antibodies (Ab3) in anti-sera. Cell-mediated immunity to tumors induced by Ab2 was investigated by a delayed-type hypersensitivity response and the mouse T-cell proliferation assay. Results Anti-idiotypic monoclonal antibodies against the monoclonal anti-NPC antibodies FC2 and HNL5 were generated that recognize NPC associated antigens. These Ab2, which were designated 2H4 and 5D3, could inhibit the binding of FC2 or HNL5 to NPC cell lines. Anti-sera from the immunized mice, which contained Ab3, could compete with FC2 or HNL5 for binding with NPC cell by a competitive inhibition assay. Mice immunized with 2H4 or 5D3 coupled with keyhole limpet hemocyanin (KLH), showed a positive and specific delayed-type hypersensitivity (DTH) reaction after stimulation by NPC cells. The mouse T cell proliferative assay indicated that there was a significantly higher proliferative response of the splenocytes in the experimental groups than that in control groups. Conclusions Anti-idiotypic antibodies 2H4 and 5D3 are Ab2 beta bearing the internal image of the epitope of NPC associated antigen. Either 2H4 or 5D3 expressing three-dimensional shapes that resemble the structure of natural antigens could induce humoral and cellular immune response.

Digitally controlled oscillator design with a variable capacitance XOR gate

A digitally controlled oscillator（DCO） using a three-transistor XOR gate as the variable load has been presented.A delay cell using an inverter and a three-transistor XOR gate as the variable capacitance is also proposed. Three-,five- and seven-stage DCO circuits have been designed using the proposed delay cell.The output frequency is controlled digitally with bits applied to the delay cells.The three-bit DCO shows output frequency and power consumption variation in the range of 3.2486-4.0267 GHz and 0.6121-0.3901 mW,respectively,with a change in the control word 111-000.The five-bit DCO achieves frequency and power of 1.8553-2.3506 GHz and 1.0202-0.6501 mW,respectively,with a change in the control word 11111-00000.Moreover,the seven-bit DCO shows a frequency and power consumption variation of 1.3239-1.6817 GHz and 1.4282-0.9102 mW,respectively, with a varying control word 1111111-0000000.The power consumption and output frequency of the proposed circuits have been compared with earlier reported circuits and the present approaches show significant improvements.

Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate

Digital controlled oscillators（DCOs） are the core of all digital phase locked loop（ADPLL） circuits. Here,DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based topology.Three,four and five bit controlled DCO with NMOS,PMOS and NMOS PMOS transistor switching networks are presented.A three-transistor XNOR gate has been used as the inverter which is used as the delay cell.Delay has been controlled digitally with a switch network of NMOS and PMOS transistors.The three bit DCO with one NMOS network shows frequency variations of 1.6141-1.8790 GHz with power consumption variations 251.9224-276.8591μW. The four bit DCO with one NMOS network shows frequency variation of 1.6229-1.8868 GHz with varying power consumption of 251.9225-278.0740μW.A six bit DCO with one NMOS switching network gave an output frequency of 1.7237-1.8962 GHz with power consumption of 251.928-278.998μW.Output frequency and power consumption results for 4 6 bit DCO circuits with one PMOS and NMOS PMOS switching network have also been presented.The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits.Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits.