Teaching Design of“ Digital Logic Design” Course Based on Blended Teaching Mode

How to design and organize the implementation of teaching is an important consideration for the quality of the course.This paper takes the“Digital Logic Design”course as an example,and carries out teaching design and practice based on the blended teaching mode.By adopting various forms such as MOOC+SPOC+theme seminars,beneficial explorations have been made in improving students’autonomous learning ability,strengthening engineering literacy,and cultivating innovation ability.

CircuitVerse:A Simulator for Teaching and Learning of Digital Logic Circuit

Digital Logic is a fundamental course of majors in electronic information.The simulation experiment is an essential measure to help students understand the principles of digital logic.It can improve the efficiency of physical experiments and decrease instrument damage caused by operating errors.CircuitVerse is an open-source and Web-based tool of circuit design and simulation for teaching purposes.And now,teachers and students in many colleges and universities use it to assist teaching and learning.Firstly,through a particular example,the features of CircuitVerse and its usage are explained.Secondly,we briefly introduce the application of CircuitVerse in our teaching as well as the following development plans.We believe that our introduction can help teachers understand the software and how to make full use of this tool.

A review on the design of ternary logic circuits

A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity,power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.

Research and practice of intelligent coal mine technology systems in China

This study considered the role of coal as China’s basic energy source and examines the development of the coal industry.We focused on the intelligent development of coal mines,and introduced the“Chinese mode”of intelligent mining in underground coal mines,which uses complete sets of technical equipment to propose classifcation and grading standards.In view of the basic characteristics and technical requirements of intelligent coal mine systems,we established a digital logic model and propose an information entity and knowledge map construction method.This involves an active information push strategy based on a knowledge demand model and an intelligent portfolio modeling and distribution method for collaborative control of coal mines.The top-level architecture of 5G+intelligent coal mine systems combines intelligent applications such as autonomous intelligent mining,human–machine collaborative rapid tunneling,unmanned auxiliary transportation,closed-loop safety control,lean collaborative operation,and intelligent ecology.Progress in intelligent mining technology was described in terms of a dynamic modifed geological model,underground 5G network and positioning technology,intelligent control of the mining height and straightness of the longwall working face,and intelligent mining equipment.The development of intelligent coal mines was analyzed in terms of its imbalances,bottlenecks,and the compatibility of large-scale systems.Implementation ideas for promoting the development of intelligent coal mines were proposed,such as establishing construction standards and technical specifcations,implementing classifcation and grading standards according to mining policy,accelerating key technology research,and building a new management and control model.

Scaling trends in energy recovery logic:an analytical approach

This paper presents an analytical model to study the scaling trends in energy recovery logic.The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage,device threshold voltage and gate oxide thickness.The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale.This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.

Research of Virtual Experiment Based on Flex and XML

In this paper, the design of a virtual experiment system based on Flex and XML is described. The system adopts threelayer architecture and it is composed of four modules. Flex is used to design user interface, and XML is used as data format between layers or modules. Data services are used to store or retrieve the information of experiment components or experiment scenes. Principles for the design of simulation engine and simulation scheduler are discussed. The design of the simulation engine for ＂Digital Logic＂ course is described in detail. The system has been implemented in the experiment teaching of Digital Logic. Teaching results and the feedback from students demonstrate that the virtual experiment system can improve the effects of experiment teaching and arouse the learning interests of students.

A low power mixed signal DC offset calibration circuit for direct conversion receiver applications

A low power mixed signal DC offset calibration （DCOC） circuit for direct conversion receiver applica- tions is designed. The proposed DCOC circuit features low power consumption, fast settling time and a small die area by avoiding the trade-off between loop response time and the high pass frequency of the DCOC servo loop in conventional analog DCOC systems. By applying the proposed DC offset correction circuitry, the output residue DC offset voltages are reduced to less than 38 mV and the DCOC loop settling time is less than 100 μs. The DCOC chip is fabricated in a standard 0.13μm CMOS technology and drains only 196 μA from a 1.2-V power supply with its chip area of only 0.372 ×0.419 mm^2.