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Development of 0.50μm CMOS Integrated Circuits Technology
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作者 Yu Shan, Zhang Dingkang and Huang Chang 《Journal of Systems Engineering and Electronics》 SCIE EI CSCD 1992年第4期7-10,2,共5页
Submicron CMOS IC technology, including triple layer resist lithography technology, RIE, LDD, Titanium Salicide, shallow junction, thin gate oxide, no bird's beak isolation and channel's multiple implantation ... Submicron CMOS IC technology, including triple layer resist lithography technology, RIE, LDD, Titanium Salicide, shallow junction, thin gate oxide, no bird's beak isolation and channel's multiple implantation doping technology have been developed. 0.50μm. CMOS integrated circuits have been fabricated using this submicron CMOS process. 展开更多
关键词 In m CmOS Integrated circuits Technology Development of 0.50 CmOS
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