Buried straw layer and plastic mulching increase microflora diversity in salinized soil

Salt stress has been increasingly constraining crop productivity in arid lands of the world. In our recent study, salt stress was aleviated and crop productivity was improved remarkably by straw layer burial plus plastic iflm mulching in a saline soil. However, its impact on the microlfora diversity is not wel documented. Field micro-plot experiments were conducted from 2010 to 2011 using four tilage methods： （i） deep tilage with plastic iflm mulching （CK）, （i） straw layer burial at 40 cm （S）, （ii） straw layer burial plus surface soil mulching with straw material （S＋S）, and （iv） plastic iflm mulching plus buried straw layer （P＋S）. Culturable microbes and predominant bacterial communities were studied; based on 16S rDNA, bacterial com-munity structure and abundance were characterized using denaturing gradient gel electrophoresis （DGGE） and polymerase chain reaction （PCR）. Results showed that P＋S was the most favorable for culturable bacteria, actinomyces and fungi and induced the most diverse genera of bacteria compared to other tilage methods. Soil temperature had signiifcant positive correlations with the number of bacteria, actinomyces and fungi （P〈0.01）. However, soil water was poorly correlated with any of the microbes. Salt content had a signiifcant negative correlation with the number of microbers, especialy for bacteria and fungi （P〈0.01）. DGGE analysis showed that the P＋S exhibited the highest diversity of bacteria with 20 visible bands folowed by S＋S, S and CK. Moreover, P＋S had the highest similarity （68%） of bacterial communities with CK. The major bacterial genera in al soil samples wereFirmicutes,Proteobacteria andActinobacteria. Given the considerable increase in microbial growth, the combined use of straw layer burial and plastic iflm mulching could be a practical option for aleviating salt stress effects on soil microbial community and thereby improving crop production in arid saline soils.

A novel high performance TFS SJ IGBT with a buried oxide layer

A novel high performance trench field stop （TFS） superjunction （S J） insulated gate bipolar transistor （IGBT） with a buried oxide （BO） layer is proposed in this paper. The BO layer inserted between the P-base and the SJ drift region acts as a barrier layer for the hole-carrier in the drift region. Therefore, conduction modulation in the emitter side of the SJ drift region is enhanced significantly and the carrier distribution in the drift region is optimized for the proposed structure. As a result, compared with the conventional TFS SJ IGBT （Conv-SJ）, the proposed BO-SJ IGBT structure possesses a drastically reduced on-state voltage drop （gce（on）） and an improved tradeoff between gee（on） and turn-off loss （Eoff）, with no breakdown voltage （BV） degraded. The results show that with the spacing between the gate and the BO layer Wo = 0.2 μm, the thickness of the BO layer Lo = 0.2 μm, the thickness of the drift region Ld = 90 μm, the half width and doping concentration of the N- and P-pillars Wn = Wp = 2.5μm and Nn = Np = 3 × 10^15 cm^-3, the Vce（on） and Eoff of the proposed structure are 1.08 V and 2.81 mJ/cm2 with the collector doping concentration Nc = 1 × 10^18 cm^-3 and 1.12 V and 1.73 mJ/cm2 with Nc = 5 × 10^17 cm^-3, respectively. However, with the same device parameters, the Vce（on） and Eoff for the Conv-SJ are 1.81 V and 2.88 mJ/cm2 with Nc= 1 × 10^18 cm^-3 and 1.98 V and 2.82 mJ/cm2 with Nc = 5 ×10^17 cm^-3, respectively. Meanwhile, the BV of the proposed structure and Conv-SJ are 1414 V and 1413 V, respectively.

New CMOS compatible super-junction LDMOST with n-type buried layer

A new super-junction lateral double diffused MOSFET （LDMOST） structure is designed with n-type charge compensation layer embedded in the p^--substrate near the drain to suppress substrate-assisted depletion effect that results from the compensating charges imbalance between the pillars in the n-type buried layer. A high electric field peak is introduced in the surface by the pn junction between the p^--substrate and n-type buried layer, which given rise to a more uniform surface electric field distribution by modulation effect. The effect of reduced bulk field （REBULF） is introduced to improve the vertical breakdown voltage by reducing the high bulk electric field around the drain, The new structure features high breakdown voltage, low on-resistance and charges balance in the drift region due to n-type buried layer.

Novel fast-switching LIGBT with P-buried layer and partial SOI

A novel silicon-on-insulator lateral insulated gate bipolar transistor(SOI LIGBT)is proposed in this paper.The proposed device has a P-type buried layer and a partial-SOI layer,which is called the BPSOI-LIGBT.Due to the electric field modulation effect generated by the P-type buried layer and the partial-SOI layer,the proposed structure generates two new peaks in the surface electric field distribution,which can achieve a smaller device size with a higher breakdown voltage.The smaller size of the device is beneficial to the fast switching.The simulation shows that under the same size,the breakdown voltage of the BPSOI LIGBT is 26%higher than that of the conventional partial-SOI LIGBT(PSOI LIGBT),and 84%higher than the traditional SOI LIGBT.When the forward voltage drop is 2.05 V,the turn-off time of the BPSOI LIGBT is 71%shorter than that of the traditional SOI LIGBT.Therefore,the proposed BPSOI LIGBT has a better forward voltage drop and turn-off time trade-off than the traditional SOI LIGBT.In addition,the BPSOI LIGBT effectively relieves the self-heating effect of the traditional SOI LIGBT.

Enhancement of Breakdown Voltage in AlGaN/GaN High Electron Mobility Transistors Using Double Buried p-Type Layers

A novel A1GaN/GaN high electron mobility transistor （HEMT） with double buried p-type layers （DBPLs） in the GaN buffer layer and its mechanism are studied. The DBPL A1GaN/GaN HEMT is characterized by two equi-long p-type GaN layers which are buried in the GaN buffer layer under the source side. Under the condition of high-voltage blocking state, two reverse p-n junctions introduced by the buried p-type layers will effectively modulate the surface and bulk electric fields. Meanwhile, the buffer leakage is well suppressed in this structure and both lead to a high breakdown voltage. The simulations show that the breakdown voltage of the DBPL structure can reach above 2000 V from 467 V of the conventional structure with the same gate-drain length of 8μm.

Synergistic Optimization of Buried Interface by Multifunctional Organic-Inorganic Complexes for Highly Efficient Planar Perovskite Solar Cells

For the further improvement of the power conversion efficiency(PCE)and stability of perovskite solar cells(PSCs),the buried interface between the perovskite and the electron transport layer is crucial.However,it is challenging to effectively optimize this interface as it is buried beneath the perovskite film.Herein,we have designed and synthesized a series of multifunctional organic-inorganic(OI)complexes as buried interfacial material to promote electron extraction,as well as the crystal growth of the perovskite.The OI complex with BF4−group not only eliminates oxygen vacancies on the SnO_(2) surface but also balances energy level alignment between SnO_(2) and perovskite,providing a favorable environment for charge carrier extraction.Moreover,OI complex with amine(−NH_(2))functional group can regulate the crystallization of the perovskite film via interaction with PbI2,resulting in highly crystallized perovskite film with large grains and low defect density.Consequently,with rational molecular design,the PSCs with optimal OI complex buried interface layer which contains both BF4−and−NH_(2) functional groups yield a champion device efficiency of 23.69%.More importantly,the resulting unencapsulated device performs excellent ambient stability,maintaining over 90%of its initial efficiency after 2000 h storage,and excellent light stability of 91.5%remaining PCE in the maximum power point tracking measurement(under continuous 100 mW cm−2 light illumination in N2 atmosphere)after 500 h.

Compound buried layer SOI high voltage device with a step buried oxide

A silicon-on-insulator （SOI） high performance lateral double-diffusion metal oxide semiconductor （LDMOS） on a compound buried layer （CBL） with a step buried oxide （SBO CBL SOI） is proposed. The step buried oxide locates holes in the top interface of the upper buried oxide （UBO） layer. Furthermore, holes with high density are collected in the interface between the polysilicon layer and the lower buried oxide （LBO） layer. Consequently, the electric fields in both the thin LBO and the thick UBO are enhanced by these holes, leading to an improved breakdown voltage. The breakdown voltage of the SBO CBL SOI LDMOS increases to 847 V from the 477 V of a conventional SOI with the same thicknesses of SOI layer and the buried oxide layer. Moreover, SBO CBL SOI can also reduce the self-heating effect.

A novel structure of a high current gain 4H-SiC BJT with a buried layer in the base

In this paper, a new structure of a 4H-SiC bipolar junction transistor （BJT） with a buried layer （BL） in the base is presented. The current gain shows an approximately 100% increase compared with that of the conventional structure. This is attributed to the creation of a built-in electric field for the minority carriers to transport in the base which is explained based on 2D device simulations. The optimized design of the buried layer region is also considered by numeric simulations.

INCREASING BREAKDOWN VOLTAGE OF LDMOST USING BURIED LAYER

A new LDMOST structure, named B-LDMOST that has a buried layer under the drain is proposed. The buried layer is not connected to the drift region, so it can optimize the vertical field distribution and increase breakdown voltage. The analysis and the simulated results show that B-LDMOST can increase breakdown voltage, with almost negligible influence on the other parameters such as on-resistance, switching time, and so on.

Positive Bias Temperature Instability Degradation of Buried InGaAs Channel nMOSFETs with InGaP Barrier Layer and Al2O3 Dielectric

Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. Well behaved split C-V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InCaP barrier layer. The direct-current Id-Vg measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive △Vg in the oncurrent region. The Id-Vg degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced aeceptor traps contain both permanent and recoverable traps. Compared with surface channel InCaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.

A high voltage Bi-CMOS compatible buffer super-junction LDMOS with an N-type buried layer

A novel buffer super-junction （S J） lateral double-diffused MOSFET （LDMOS） with an N-type buried layer （NB） is proposed. An N- buffer layer is implemented under the SJ region and an N-type layer is buried in the P substrate. Firstly, the new electric field peak introduced by the p-n junction of the P substrate and the N-type buried layer modulates the surface electric field distribution. Secondly, the N-buffer layer suppresses the substrate assisted depletion effect. Both of them improve the breakdown voltage （BV）. Finally, because of the shallow depth of the SJ region, the NB buffer SJ-LDMOS is compatible with Bi-CMOS technology. Simulation results indicate that the average value of the surface lateral electric field strength of the NB buffer SJ-LDMOS reaches 23 V/μm at 15/μm drift length which results in a BV of 350 V and a specific on-resistance of 21 mΩ·cm2.

Electric field modulation technique for high-voltage AlGaN/GaN Schottky barrier diodes

A novel structure of AIGaN/GaN Schottky barrier diode （SBD） featuring electric field optimization techniques of anode-connected-field-plate （AFP） and magnesium-doped p-type buried layer under the two-dimensional electron gas （2DEG） channel is proposed. In comparison with conventional A1GaN/GaN SBDs, the magnesium-doped p-type buried layer in the proposed structure can provide holes that can help to deplete the surface 2DEG. As a result, surface field strength around the electrode edges is significantly suppressed and the electric field along the channel is distributed more evenly. Through 2D numerical analysis, the AFP parameters （field plate length, LAFP, and field plate height, TAFP） and p-type buried layer parameters （p-type layer concentration, Np, and p-type layer thickness, Tp） are optimized to achieve a three-equal-peak surface channel field distribution under exact charge balance conditions. A novel structure with a total drift region length of 10.5 μm and a magnesium-doped p-type concentration of 1 × 10^17 cm 3 achieves a high breakdown voltage （VB） of 1.8 kV, showing 5 times improvement compared with the conventional SBD with the same device dimension.

A-188 V 7.2Ω·mm^2,P-channel high voltage device formed on an epitaxy-SIMOX substrate

This paper proposes a new n＋-charge island （NCI） P-channel lateral double diffused metal-oxide semiconductor （LDMOS） based on silicon epitaxial separation by implantation oxygen （E-SIMOX） substrate. Higher concentration self-adapted holes resulting from a vertical electric field are located in the spacing of two neighbouring n＋-regions on the interface of a buried oxide layer, and therefore the electric field of a dielectric buried layer （EI） is enhanced by these holes effectively, leading to an improved breakdown voltage （BV）. The VB and E! of the NCI P-channel LDMOS increase to -188 V and 502.3 V/μm from -75 V and 82.2 V/μm of the conventional P-channel LDMOS with the same thicknesses SOI layer and the buried oxide layer, respectively. The influences of structure parameters on the proposed device characteristics are investigated by simulation. Moreover, compared with the conventional device, the proposed device exhibits low special on-resistance.

A high-voltage SOI MOSFET with a compensation layer on the trenched buried oxide layer

A new silicon-on-insulator(SOI) high-voltage MOSFET structure with a compensation layer on the trenched buried oxide layer(CL T-LDMOS) is proposed.The high density inverse interface charges at the top surface of the buried oxide layer(BOX) enhance the electric field in the BOX and a uniform surface electric field profile is obtained,which results in the enhancement of the breakdown voltage(BV).The compensation layer can provide additional P-type charges,and the optimal drift region concentration is increased in order to satisfy the reduced surface electric field(RESURF) condition.The numerical simulation results indicate that the vertical electric field in the BOX increases to 6 MV/cm and the B V of the proposed device increases by 300%in comparison to a conventional SOI LDMOS,while maintaining low on-resistance.

A novel complementary N^+-charge island SOI high voltage device

A new complementary interface charge island structure of SOI high voltage device（CNI SOI） and its model are presented.CNI SOI is characterized by equidistant high concentration n＋-regions on the top and bottom interfaces of dielectric buried layers.When a high voltage is applied to the device,complementary hole and electron islands are formed on the two n＋-regions on the top and bottom interfaces.The introduced interface charges effectively increase the electric field of the dielectric buried layer（EI） and reduce the electric field of the silicon layer（ES）,which result in a high breakdown voltage（BV）.The influence of structure parameters and its physical mechanism on breakdown voltage are investigated for CNI SOI.EI=731 V/μm and BV=750 V are obtained by 2D simulation on a 1-μm-thick dielectric layer and 5-μm-thick top silicon layer.Moreover,enhanced field EI and reduced field ES by the accumulated interface charges reach 641.3 V/μm and 23.73 V/μm,respectively.