Fuzzy Based Adaptive Deblocking Filters at Low-Bitrate HEVC Videos for Communication Networks

In-loop filtering significantly helps detect and remove blocking artifacts across block boundaries in low bitrate coded High Efficiency Video Coding(HEVC)frames and improves its subjective visual quality in multimedia services over communication networks.However,on faster processing of the complex videos at a low bitrate,some visible artifacts considerably degrade the picture quality.In this paper,we proposed a four-step fuzzy based adaptive deblocking filter selection technique.The proposed method removes the quantization noise,blocking artifacts and corner outliers efficiently for HEVC coded videos even at low bit-rate.We have considered Y(luma),U(chromablue),and V(chroma-red)components parallelly.Finally,we have developed a fuzzy system to detect blocking artifacts and use adaptive filters as per requirement in all four quadrants,namely up 45◦,down 45◦,up 135◦,and down 135◦across horizontal and vertical block boundaries.In this context,experimentation is done on a wide variety of videos.An objective and subjective analysis is carried out with MATLAB software and Human Visual System(HVS).The proposed method substantially outperforms existing postprocessing deblocking techniques in terms of YPSNR and BD_rate.In the proposed method,we achieved 0.32–0.97 dB values of YPSNR.Our method achieved a BD_rate of+1.69%for the luma component,−0.18%(U)and−1.99%(V)for chroma components,respectively,with respect to the stateof-the-art methods.The proposed method proves to have low computational complexity and has better parallel processing,hence suitable for a real-time system in the near future.

Reconfigurable design of deblocking filter for variable block sizes

Based on the flexible quadtree partition structure of coding tree units(CTUs),the deblocking filter(DBF)in high efficiency video coding(HEVC)consumes a lot of resources when implemen-ted by hardware.It is difficult to achieve flexible switching between different sizes of coding blocks.Aiming at this problem,a reconfigurable implementation of DBF is proposed.Based on the dynamic programmable reconfigurable video array processor(DPRAP)with context switch reconfiguration mechanism,the runtime flexible switching of two coding block sizes is realized.The experimental results show that the highest work-frequency reaches 151.4 MHz.Compared with the dedicated hardware architecture scheme,the resource consumption can be reduced by 28.1%while realizing the dynamic switching between algorithms of two coding block sizes.Compared with the results of HM16.0,by using a complete I-frame for testing,the average peak signal-to-noise ratio(PSNR)of the reconfigurable implementation proposed in this paper has increased by 3.0508 dB,the coding quality has improved to a certain extent.

Parallel processing architecture of H.264 adaptive deblocking filters

In H.264,computational complexity and memory access of deblocking filters are variable,dependent on video contents.This paper proposes a VLSI architecture of deblocking filters with adaptive dynamic power,which avoids redundant computations and memory accesses by precluding the blocks that can be skipped.The vertical and horizontal edges are simulta-neously processed in an advanced scan order to speed up the decoder.As a result,dynamic power of the proposed architecture can be reduced adaptively(up to about 89%) for different videos,and the off-chip memory access is improved when compared to previous designs.Moreover,the processing capability of the proposed architecture is in particular appropriate for real-time deblocking of high-definition television(HDTV,1920×1080 pixels/frame,60 frames/s video signals) video operation at 62 MHz.Using the proposed architecture,power can be reduced by up to about 89% and processing time by from 25% to 81% compared with previous designs.

Parallel-pipelined Architecture of H.264 Deblocking Filter with Adaptive Dynamic Power

In H.264,the computational complexity and memory access of deblocking filter are variable and depend on the video contents. In this paper,a pipelined VLSI architecture of deblocking filter with adaptive dynamic power is proposed. It avoids redundant computations and memory access by precluding the blocks which can be skipped. And the vertical and horizontal edges are simultaneously processed in an advanced scan order to speed up the decoder. As a result,the dynamic power of the proposed architecture can be reduced (up to about 89%) adaptively for different videos. And the off-chip memory access is improved compared to the previous designs. Moreover,the processing capability of the proposed architecture is very appropriate for real-time deblocking of high-definition television (HDTV,1920× 1080 pixel/frame,30 frame/s video signals) video operation at 38 MHz,which significantly outperforms the previous designs from 1.25 times to 4.8 times.

Design of adaptive deblocking filter for H.264/AVC decoder SOC

In this article, a design for the adaptive deblocking filter is proposed. To understand the real-time performance, a FILTER unit that can process eight pixels beside an edge simultaneously is applied in this design to increase filtering efficiency, and local memory is used to store all temporary data generated by the FILTER to reduce access to system bus. The filter makes every 4×4 sample block pipelined through the process units and achieves an efficiency of 80% for both the FILTER unit and the bus access unit. It can fulfill filtering process for a crystallographic information file （CIF, 352×288） format picture in 95 k clock cycles. The proposed design is part of a H.264/AVC decoder system-on-chip （SOC）, which is fabricated in 0.18 μm complementary metal oxide semiconductor （CMOS） process. The filter module consists of 60 k gates and 25.7 kb static random access memory （SRAM） and it can filter a macro-block in 240 clock cycles.

JPEG stream soft-decoding technique based on autoregressive modeling

This paper introduces a new model-based soft decoding techniqt, e to restore the widely used joint photographic expert group （JPEG） streams. The image is modeled as a two dimensional （2D） piecewise stationary autoregressive process, and the decoding task is formulated as a constrained optimization problem. All the constraints are given by the quantization intervals which available at the decoder freely. The autoregressive model serves as an important regularization term of the objective function of the optimization, and the model parameters are solved on the decoded image locally using a weighted total least square method. In addition, a novel bilateral dualside weighting scheme is proposed to minimize the influence of the blocking artifact on the accuracy of parameter estimation. Extensive experimental results suggest that the proposed algorithm systematically improves the quality of JPEG images and also outperforms existing JPEG postprocessing algorithms in a wide bit-rate range both in terms of peak signal-to-noise ratio （PSNR） and subjective quality

Low-Complexity Tools in AVS Part 7

Audio Video coding Standard （AVS） is established by the AVS Working Group of China. The main goal of AVS part 7 is to provide high compression performance with relatively low complexity for mobility applications. There are 3 main low-complexity tools： deblocking filter, context-based adaptive 2D-VLC and direct intra prediction. These tools are presented and analyzed respectively. Finally, we compare the performance and the decoding speed of AVS part 7 and H.264 baseline profile. The analysis and results indicate that AVS part 7 achieves similar performance with lower cost.