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A 430 mW 16 b 170 MS/s CMOS pipelined ADC with 77.2 dB SNR and 97.6 dB SFDR
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作者 张辉 李丹 +6 位作者 万磊 张辉 王海军 高远 朱腓利 王紫琪 丁学欣 《Journal of Semiconductors》 EI CAS CSCD 2016年第3期88-94,共7页
A 16-bit 170 MS/s pipelined ADC implemented in 0.18 m CMOS process is presented in this paper. An improved digital calibration method and a linearized sampling front-end are employed to achieve a high SFDR. The enlarg... A 16-bit 170 MS/s pipelined ADC implemented in 0.18 m CMOS process is presented in this paper. An improved digital calibration method and a linearized sampling front-end are employed to achieve a high SFDR. The enlarged full scale range makes it possible to obtain a high SNR with smaller sampling capacitors, thus achieving higher speed and low power. This ADC attains an SNR of 77.2 d BFS, an SFDR of 97.6 d Bc for a 10 MHz input signal, while preserving an SFDR 〉 80 d Bc up to 300 MHz input frequency. The ADC consumes 430 mW from a1.8 V supply and occupies a 17 mm^2 active area. 展开更多
关键词 pipelined ADC calibration SHA-less if sampling
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