The Serial Communication Based on Multithreading Technique of Windows

Present a kind of method which is used to communicate between serial serial port and peripheral equipment dynamicly and real-time using multithreading technique based on the basic principle of communication and multitasking mechanism in the circumstance of Windows. This method resolves the question of Real-time answering in the serial communication validly, reduces losing rate of data and improves reliability of system. This article presents a general method used in the serial communication which is practical.

A Multithreaded CGRA for Convolutional Neural Network Processing

Convolutional neural network (CNN) is an essential model to achieve high accuracy in various machine learning applications, such as image recognition and natural language processing. One of the important issues for CNN acceleration with high energy efficiency and processing performance is efficient data reuse by exploiting the inherent data locality. In this paper, we propose a novel CGRA (Coarse Grained Reconfigurable Array) architecture with time-domain multithreading for exploiting input data locality. The multithreading on each processing element enables the input data reusing through multiple computation periods. This paper presents the accelerator design performance analysis of the proposed architecture. We examine the structure of memory subsystems, as well as the architecture of the computing array, to supply required data with minimal performance overhead. We explore efficient architecture design alternatives based on the characteristics of modern CNN configurations. The evaluation results show that the available bandwidth of the external memory can be utilized efficiently when the output plane is wider (in earlier layers of many CNNs) while the input data locality can be utilized maximally when the number of output channel is larger (in later layers).

Simultaneous Multithreading Fault Tolerance Processor

Transient fault detection mechanism is added to simultaneous multithreading architecture. By exploiting both ILP (Instruction Level Parallelism) and TLP (Thread Level Parallelism), Simultaneous Multithreading (SMT) Fault Tolerance Processor can be expected to achieve better tradeoff between performance and hardware cost than traditional Fault Tolerance Processors. Detailed simulations of 3 of SPEC95 benchmarks show that executing two redundant programs on the fault-tolerant microarchitecture takes only 40%–61%longer than running a single version of the program. The new instruction fetch algorithm enhances the performance by 0.4%～1%to most of the benchmarks we choose randomly.

Redundant Multithreading Architecture Overview

To overcome the ever-increasing susceptibility to transient-fault in processors, various redundant multithreading （RMT） architectures have been proposed, which is becoming a most effective approach for detecting and recovering from transient-fault. This paper surveys a wide range of RMT architectures-from the original AR-SMT（A-stream R-stream Simultaneous MultiThreading） to the most-recent SD-SRT （Slack-Decode Simultaneous Redundant Threading）, presenting traverse analyses and comparisons among them, and hereby demonstrates its evolution and tendency. Finally, some directions and suggestions are put forward for the further RMT research and development.

Dynamic Power Dissipation Control Method for Real-Time Processors Based on Hardware Multithreading

In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware multithread is discussed and a novel dynamic multithreaded architecture is proposed. The proposed architecture saves the energy wasted by removing idle threads without manipulation on the original architecture, fulfills a seamless switching mechanism which protects active threads and avoids pipeline stall during power mode switching. The report of an implemented dynamic multithreaded processor with 45 nm process from synthesis tool indicates that the area of dynamic multithreaded architecture is only 2.27% higher than the static one in achieving dynamic power dissipation, and consumes 1.3% more power in the same peak performance.

An Efficient and Flexible Deterministic Framework for Multithreaded Programs

Determinism is very useful to multithreaded programs in debugging, testing, etc. Many deterministic ap- proaches have been proposed, such as deterministic multithreading （DMT） and deterministic replay. However, these sys- tems either are inefficient or target a single purpose, which is not flexible. In this paper, we propose an efficient and flexible deterministic framework for multithreaded programs. Our framework implements determinism in two steps： relaxed determinism and strong determinism. Relaxed determinism solves data races eificiently by using a proper weak memory consistency model. After that, we implement strong determinism by solving lock contentions deterministically. Since we can apply different approaches for these two steps independently, our framework provides a spectrum of deterministic choices, including nondeterministic system （fast）, weak deterministic system （fast and conditionally deterministic）, DMT system, and deternfinistic replay system. Our evaluation shows that the DMT configuration of this framework could even outperform a state-of-the-art DMT system.

Optimization of thread partitioning parameters in speculative multithreading based on artificial immune algorithm

Thread partition plays an important role in speculative multithreading （SpMT） for automatic parallelization of ir- regular programs. Using unified values of partition parameters to partition different applications leads to the fact that every ap- plication cannot own its optimal partition scheme. In this paper, five parameters affecting thread partition are extracted from heuristic rules. They are the dependence threshold （DT）, lower limit of thread size （TSL）, upper limit of thread size （TSU）, lower limit of spawning distance （SDL）, and upper limit of spawning distance （SDU）. Their ranges are determined in accordance with heuristic rules, and their step-sizes are set empirically. Under the condition of setting speedup as an objective function, all com- binations of five threshold values form the solution space, and our aim is to search for the best combination to obtain the best thread granularity, thread dependence, and spawning distance, so that every application has its best partition scheme. The issue can be attributed to a single objective optimization problem. We use the artificial immune algorithm （AIA） to search for the optimal solution. On Prophet, which is a generic SpMT processor to evaluate the performance of multithreaded programs, Olden bench- marks are used to implement the process. Experiments show that we can obtain the optimal parameter values for every benchmark, and Olden benchmarks partitioned with the optimized parameter values deliver a performance improvement of 3.00% on a 4-core platform compared with a machine learning based approach, and 8.92% compared with a heuristics-based approach.

Chip Multithreaded Consistency Model

Multithreaded technique is the developing trend of high performance processor. Memory consistency model is essential to the correctness, performance and complexity of multithreaded processor. The chip multithreaded consistency model adapting to multithreaded processor is proposed in this paper. The restriction imposed on memory event ordering by chip multithreaded consistency is presented and formalized. With the idea of critical cycle built by Wei-Wu Hu, we prove that the proposed chip multithreaded consistency model satisfies the criterion of correct execution of sequential consistency model. Chip multithreaded consistency model provides a way of achieving high performance compared with sequential consistency model and easures the compatibility of software that the execution result in multithreaded processor is the same as the execution result in uniprocessor. The implementation strategy of chip multithreaded consistency model in Godson-2 SMT processor is also proposed. Godson-2 SMT processor supports chip multithreaded consistency model correctly by exception scheme based on the sequential memory access queue of each thread.

Hardwired Logic and Multithread Design in Network Processors

High-performance network processors are expected to play an important role in future high-speed routers. This paper focuses on two representative techniques needed for high-performance network processors: hardwired logic design and multithread design. Using hardwired logic, this paper compares a single-thread design with a multithread design, and proposes general models and principles to analyze the clock frequency and the resource cost for these environments. Then, two IP header processing schemes, one in single-thread mode and the other in double-thread mode, are developed using these principles and the implementation results verified the theoretical calculation.

PsmArena:Partitioned Shared Memory for NUMA-Awareness in Multithreaded Scientific Applications

The Distributed Shared Memory(DSM)architecture is widely used in today’s computer design to mitigate the ever-widening processing-memory gap,and it inevitably exhibits Non-Uniform Memory Access(NUMA)to shared-memory parallel applications.Failure to adapt to the NUMA effect can significantly downgrade application performance,especially on today’s manycore platforms with tens to hundreds of cores.However,traditional approaches such as first-touch and memory policy fall short in false page-sharing,fragmentation,or ease of use.In this paper,we propose a partitioned shared-memory approach that allows multithreaded applications to achieve full NUMA-awareness with only minor code changes and develop an accompanying NUMA-aware heap manager which eliminates false page-sharing and minimizes fragmentation.Experiments on a 256-core cc-NUMA computing node show that the proposed approach helps applications to adapt to NUMA with only minor code changes and improves the performance of typical multithreaded scientific applications by up to 4.3 folds with the increased use of cores.

Multithread纤细网络支撑设计书桌

"multithread"系列的每件家具都是从一个水平面开始的一一这个面可以是桌面,架子,书桌等等——它由一个连接杆组成的纤细网络支撑。这件产品是由慕尼黑和斯德哥尔摩事务所kram/weisshaar(reed

多工位硅胶圈缺陷在线视觉检测系统研究

硅胶圈检测由于缺陷具有种类多、易变形、复杂性高等特点,通过提出多工位、多角度、不同打光方式结合的基于视觉的机电检测系统来解决这类产品的检测问题。整个检测系统的图像处理使用了基于OpenCV库按照实际项目需求进行改进,使用滤波算子、阈值分割和形态学方法。使用VGG16卷积神经网络训练模型在小样本条件对三种缺陷分类和传统视觉检测方法得到的准确率进行对照实验。在小样本下传统机器视觉的检测准确率>98%,优于深度学习的方法。通过Qt完成UI界面的设计。该软件系统使用多线程设计模式编写,并提出了一种多工位循环剔除新方法,具备在线检测计数和剔除功能。就一种特定的硅胶圈产品检测进行实际实验和测试,验证了本系统的可靠性和实用性。

Parallelizable Calculation of Observables Values on Analog Quantum Computer

The superiority of hypothetical quantum computers is not due to faster calculations but due to different schemes of calculations running on special hardware. The core of quantum computing follows the way a state of a quantum system is defined when basic things interact with each other. In conventional approach it is implemented through tensor product of qubits. In the geometric algebra formalism simultaneous availability of all the results for non-measured observables is based on the definition of states as points on three-dimensional sphere.

Multi-Plate Microbial Monitoring Terminal Based on Raspberry Pi 4B

We utilized Raspberry Pi 4B to develop a microbial monitoring system to simplify the microbial image-capturing process and facilitate the informatization of microbial observation results.The Raspberry Pi 4B firmware,developed under Python on the Linux platform,achieves sum verification of serial data,file upload based on TCP protocol,control of sequence light source and light valve,real-time self-test based on multithreading,and an experiment-oriented file management method.The system demonstrated improved code logic,scheduling,exception handling,and code readability.

基于多线程的岩心图像超维重建快速算法

针对基于邻域块匹配的超维算法在重建过程中每次只能对1个待重建块进行重建,并且字典搜索过程十分耗时导致重建效率低的问题,本文提出了2种方法来对基于邻域块匹配的超维算法进行计算速度的优化.首先,将分区域重建应用到基于邻域块匹配的超维算法中,提出了分区域并行重建算法,实现了对多个待重建块同时进行重建;其次,在对每次字典元素搜索的过程中,使用了字典并行搜索,实现了这一过程的加速;最后将这2种方法进行结合,并且通过高中低3种不同孔隙度的训练图像生成的字典来对二维参考图像进行多次重建.通过将本文提出的算法、基于邻域块匹配的超维算法以及一些传统重建算法的重建结果和真实岩心三维结构的统计特征参数进行对比并且将不同重建算法的重建时间进行对比,来验证本文改进的超维算法的有效性.

结合维诺区域分割和路径优化的路径规划算法

在一些较大面积的建筑物内,移动机器人的路径规划算法的效率仍然面临着较大的挑战。针对这类工作场景,提出了一种结合维诺区域分割和路径优化的路径规划算法(Voronoi region segmentation and path optimization,VSO),实现在大规模室内场景下的快速路径规划。该算法使用广义维诺图(generalized Voronoi graph,GVG)从地图中构建拓扑图,在拓扑图上可以快速获得初始启发式路径。通过将采样过程约束在初始路径周围的区域,减少了对工作空间的过度探索。在此基础上,选择路径点将采样区域划分为多个子区域,之后在子区域中并行搜索路径来减少搜索空间并提升搜索速度。最后将连接各个子区域内的路径作为结果路径,并使用优化算法来平滑最终路径。仿真实验与机器人实验验证了该算法的实用性与有效性。

多线程C程序内存安全性动态分析方法

随着软件结构越来越复杂以及其要求更高级别的并发量,出现了越来越多的多线程程序,同时C语言程序缺乏检测其内存安全的能力,进而导致C语言实现的程序可能会存在较多的隐藏漏洞,因此对多线程C程序的内存安全检测尤为的重要。较为前沿且可靠的检测内存安全的技术主要为动态分析技术,且现在对于多线程C程序内存安全检测的工具不是特别完善,错误检测不完全,性能不是很高。因此提出了基于指针的动态分析技术,同时结合无锁技术、源代码插桩技术实现了工具Movec来对多线程C程序的内存安全性进行检测,并且选取专业测试集来进行实验,验证了本工具对于多线程C程序检测内存安全是有效的,检测的错误更多且性能较为优秀。

基于RocketMQ跨电力安全区的HTTP异步传输

电力监控系统中禁止低安全区主动访问高安全区的规定给需要相应功能的系统带来挑战。文章提出了一种基于RocketMQ跨电力安全区的HTTP异步传输方案,低安全区对HTTP请求进行唯一编码、缓存至请求队列,高安全区主动消费请求队列重新组装请求,并将请求结果推送至结果队列,利用多线程技术保证数据传输的及时有效。真实场景下的验证结果表明,基于RocketMQ跨电力安全区的HTTP异步传输方案满足了低安全区主动访问高安全区的需求,增强了电力系统安全分区之间的信息共享能力。

跨平台访问端传感网络串口通信多线程实现

串口是外部串行设备与计算机之间的关键数据传输通道,由于跨平台访问端的传感器数据来自不同平台,具有显著独立性,融合难度较大,直接影响多线程通信效率。提出一种针对跨平台访问端传感网络的串口通信多线程实现方法。构建跨平台访问端,采用统计概率置信度算法,修正或剔除传感网络数据中的异常值。从时间相关性和空间相关性,完成传感网络的数据融合。依据信标时序补偿网络时钟同步法、父子链路时序轮转调度法,分配多线程执行信息传输,实现跨平台访问端传感网络串口多线程通信。实验表明:当线程数量由1增加至16时,在低网络流量和高网络流量负载情况下,所提方法的传感网络延迟可控制在0.53 ms以内。且在相同传输错漏率下,所提方法的进程平均超限步数始终更低。