A High-Elasticity Router Architecture with Software Data Plane and Flow Switching Plane Separation

Routers have traditionally been architected as two elements: forwarding plane and control plane through For CES or other protocols. Each forwarding plane aggregates a fixed amount of computing, memory, and network interface resources to forward packets. Unfortunately, the tight coupling of packet-processing tasks with network interfaces has severely restricted service innovation and hardware upgrade. In this context, we explore the insightful prospect of functional separation in forwarding plane to propose a next-generation router architecture, which, if realized, can provide promises both for various packet-processing tasks and for flexible deployment while solving concerns related to the above problems. Thus, we put forward an alternative construction in which functional resources within a forwarding plane are disaggregated. A forwarding plane is instead separated into two planes: software data plane(SDP) and flow switching plane(FSP), and each plane can be viewed as a collection of "building blocks". SDP is responsible for packet-processing tasks without its expansibility restricted with the amount and kinds of network interfaces. FSP is in charge of packet receiving/transmitting tasks and can incrementally add switching elements, such as general switches, or even specialized switches, to provide network interfaces for SDP. Besides, our proposed router architecture uses network fabrics to achievethe best connectivity among building blocks,which can support for network topology reconfiguration within one device.At last,we make an experiment on our platform in terms of bandwidth utilization rate,configuration delay,system throughput and execution time.

Design of an unbuffered switch for network on-chip

In the complex multicore chip system,network on-chip(NoC)is viewed as a kind of system interconnection that can substitute the traditional interconnect networks,which will improve the system performance and communication efficiency.With regard to the complex and large scale NoC,simple and efficient routing nodes are the critical factors to achieve low-cost and low-congestion communication performance.This paper proposes an unbuffered switch architecture and makes detailed analysis of the mechanism of buffer in the switch architecture.According to the simulation results,the S-mesh using the unbuffered switch architecture is better in terms of the optimal performance in message latency than some typical NoC architectures,such as 2D-mesh,Fat-tree,Butterfly,Octagon and so on.The synthesis results of design compiler indicate that the unbuffered switch has obvious advantages of achieving cost and operating speed for the chips.

High Performance Interconnect Network for Tianhe System

In this paper, we present the Tianhe-2 interconnect network and message passing services. We describe the architecture of the router and network interface chips, and highlight a set of hardware and software features effectively supporting high performance communications, ranging over remote direct memory access, collective optimization, hardwareenable reliable end-to-end communication, user-level message passing services, etc. Measured hardware performance results are also presented.