A new early-late synchronizer is proposed to improve tracking speed. The performance of the traditional early-late synchronizer is analyzed in detail, the result shows that the different location and length of integra...A new early-late synchronizer is proposed to improve tracking speed. The performance of the traditional early-late synchronizer is analyzed in detail, the result shows that the different location and length of integral period can influence the discriminator characteristic, an improved integral structure is provided which can tracking the synchronization error better. According to the good tracking performance of Kalman filter, a new loop filter is designed. The new early-late synchronizer adopts both the new integral structure and the new loop filter. The analysis with loop theory and simulation results in Simulink show that the new bit synchronizer possesses higher tracking speed than the traditional early-late synchronizer.展开更多
Polarization division multiplexing (PDM) can double the spectral efficiency of an optical transmission system. By means of simulation, the 2x40Gbit/s NRZ PDM system performance under polarization mode dispersion (PMD)...Polarization division multiplexing (PDM) can double the spectral efficiency of an optical transmission system. By means of simulation, the 2x40Gbit/s NRZ PDM system performance under polarization mode dispersion (PMD) and chromatic dispersion has been investigated. To realize the best performance, the bit slots of the two channels should be synchronized.展开更多
This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter （ADC） A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only...This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter （ADC） A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm^2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.展开更多
基金Sponsored bythe Ministerial Level Advanced Research Foundation(2000)
文摘A new early-late synchronizer is proposed to improve tracking speed. The performance of the traditional early-late synchronizer is analyzed in detail, the result shows that the different location and length of integral period can influence the discriminator characteristic, an improved integral structure is provided which can tracking the synchronization error better. According to the good tracking performance of Kalman filter, a new loop filter is designed. The new early-late synchronizer adopts both the new integral structure and the new loop filter. The analysis with loop theory and simulation results in Simulink show that the new bit synchronizer possesses higher tracking speed than the traditional early-late synchronizer.
文摘Polarization division multiplexing (PDM) can double the spectral efficiency of an optical transmission system. By means of simulation, the 2x40Gbit/s NRZ PDM system performance under polarization mode dispersion (PMD) and chromatic dispersion has been investigated. To realize the best performance, the bit slots of the two channels should be synchronized.
文摘This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter （ADC） A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm^2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.
