Fuzzy System Design Using Current Amplifier for 20 nm CMOS Technology

In the recent decade,different researchers have performed hardware implementation for different applications covering various areas of experts.In this research paper,a novel analog design and implementation of different steps of fuzzy systems with current differencing buffered amplifier(CDBA)are proposed with a compact structure that can be used in many signal processing applications.The proposed circuits are capable of wide input current range,simple structure,and are highly linear.Different electrical parameters were compared for the proposed fuzzy system when using different membership functions.The novelty of this paper lies in the electronic implementation of different steps for realizing a fuzzy system using current amplifiers.When the power supply voltage of CDBA is 2V,it results in 155mW,power dissipation;4.615KΩ,input resistance;366KΩ,output resistances;and 189.09 dB,common-mode rejection ratio.A 155.519 dB,voltage gain,and 0.76V/μs,the slew rate is analyzed when the power supply voltage of CDBAis 3V.The fuzzy system is realized in 20nm CMOS technology and investigated with an output signal of high precision and high speed,illustrating that it is suitable for realtime applications.In this research paper,a consequence of feedback resistance on the adder circuit and the defuzzified circuit is also analyzed and the best results are obtained using 100K resistance.The structure has a low hardware complexity leading to a low delay and a rather high quality.

Multifunction Filter Employing Current Differencing Buffered Amplifier

This paper proposes a new filter biquad circuit, which utilizes three Current Differencing Buffered Amplifiers (CDBA), two capacitors and five resistors, and operates in the trans-resistance mode. This multi-input and single-output multifunction filter uses only grounded capacitors. All the employed resistors are either grounded or virtually grounded, which is an important parameter for its implementation as an integrated circuit. The circuit enjoys independent tunability of angular frequency and bandwidth. The 0.5 μm technology process parameters have been utilized to test and verify the performance characteristics of the circuit using PSPICE. The non-ideal analysis and sensitivity analysis, transient response, Monte-Carlo analysis and calculations of total harmonic distortion have also been shown.

Cache Memory Design for Single Bit Architecture with Different Sense Amplifiers

Most modern microprocessors have one or two levels of on-chip caches to make things run faster,but this is not always the case.Most of the time,these caches are made of static random access memory cells.They take up a lot of space on the chip and use a lot of electricity.A lot of the time,low power is more important than several aspects.This is true for phones and tablets.Cache memory design for single bit architecture consists of six transistors static random access memory cell,a circuit of write driver,and sense amplifiers(such as voltage differential sense amplifier,current differential sense amplifier,charge transfer differential sense amplifier,voltage latch sense amplifier,and current latch sense amplifier,all of which are compared on different resistance values in terms of a number of transistors,delay in sensing and consumption of power.The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34μW of power which shows that power is reduced up to 83%,77.75%reduction in the case of the current differential sense amplifier,39.62%in case of charge transfer differential sense amplifier and 50%in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture.Furthermore,power reduction techniques are applied over different blocks of cache memory architecture to optimize energy.The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078μW of power,i.e.,reduce 28%more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.

Current-Controlled CFTA Based Fractional Order Quadrature Oscillators

This paper presents a study of fractional order quadrature oscillators based on current-controlled current follower transconductance amplifiers (CCCFTA). The design realisation and performance of the fractional order quadrature oscillators have been presented. The quadrature oscillators are constructed using three fractional capacitors of orders α = 0.5. The fractional capacitor is not available on the market or in the PSPICE program. Fortunately, the fractional capacitor can be realised by using the approximate method for the RC ladder network approximation. The oscillation frequency and oscillation condition can be electronically/orthogonally controlled via input bias currents. Due to high-output impedances, the proposed circuit enables easy cascading in current-mode (CM). The PSPICE simulation results are depicted, and the given results agree well with the anticipated theoretical outcomes.

Lower-power, high-linearity class-AB current-mode programmable gain amplifier

A novel class-AB implementation of a current-mode programmable gain amplifier （CPGA） including a current-mode DC offset cancellation loop is presented. The proposed CPGA is based on a current amplifier and provides a current gain in a range of 40 dB with a 1 dB step. The CPGA is characterized by a wide range of current gain variation, a lower power dissipation, and a small chip size. The proposed circuit is fabricated using a 0.18 μm CMOS technology. The CPGA draws a current of less than 2.52 mA from a 1.8 V supply while occupying an active area of 0.099μm2. The measured results show an overall gain variation from 10 to 50 dB with a gain error of less than 0.40 dB. The OP1dB varies from 11.80 to 13.71 dBm, and the 3 dB bandwidth varies from 22.2 to 34.7 MHz over the whole gain range.

Low voltage floating gate MOSFET based current differencing transconductance amplifier and its applications

This article presents a low voltage low power configuration of current differencing transconductance amplifier（CDTA）based on floating gate MOSFET.The proposed CDTA variant operates at lower supply voltage±1.4 V with total static power dissipation of 2.60 mW due to the low voltage feature of floating gate MOSFET.High transconductance up to 6.21 mA/V is achieved with extended linear range of the circuit i.e.±130μA.Two applications are illustrated to demonstrate the effectiveness of the proposed active block.A quadrature oscillator is realized using FGMOS based CDTA,two capacitors,and a resistor.The resistor is implemented using two NMOSFETs to provide high linearity and tunablility.Another application is the Schmitt trigger circuit based on the proposed CDTA variant.All circuits are simulated by using SPICE and TSMC 130 nm technology.

A low-voltage sense amplifier with two-stage operational amplifier clamping for flash memory

A low-voltage sense amplifier with reference current generator utilizing two-stage operational amplifier clamp structure for flash memory is presented in this paper,capable of operating with minimum supply voltage at1 V.A new reference current generation circuit composed of a reference cell and a two-stage operational amplifier clamping the drain pole of the reference cell is used to generate the reference current,which avoids the threshold limitation caused by current mirror transistor in the traditional sense amplifier.A novel reference voltage generation circuit using dummy bit-line structure without pull-down current is also adopted,which not only improves the sense window enhancing read precision but also saves power consumption.The sense amplifier was implemented in a flash realized in 90 run flash technology.Experimental results show the access time is 14.7 ns with power supply of 1.2 V and slow corner at 125℃.

Ultra-low noise measurements of nanopore-based single molecular detection

Nanopore is an ultra-sensitive electrochemical technique for single molecular detection in confined space. To suppress the noise in detection of the weak current of nanopore, we investigated the influence of membrane capacitance and applied voltage on the noise of the current signal by model analysis, simulation and experiment. The obtained results demonstrated that membrane capacitance affects the noise by amplifying the noise of the applied voltage. Therefore, suppression of applied voltage noise is an efficient approach for reducing the noise in nanopore detection. Here, we developed an ultra-low noise instrument system for detecting the single molecule signal in nanopores. As demonstrated by nanopore experiments, the p-p noise of the developed system during the recording is reduced to 3.2B pA using the filter of 5 kHz. Therefore, the developed system could be applied in highly sensitive nanopore detection.