Current-collapse suppression and leakage-current decrease in AlGaN/GaN HEMT by sputter-TaN gate-dielectric layer

In this paper, we explore the electrical characteristics of high-electron-mobility transistors(HEMTs) using a TaN/AlGaN/GaN metal insulating semiconductor(MIS) structure. The high-resistance tantalum nitride(TaN) film prepared by magnetron sputtering as the gate dielectric layer of the device achieved an effective reduction of electronic states at the TaN/AlGaN interface, and reducing the gate leakage current of the MIS HEMT, its performance was enhanced. The HEMT exhibited a low gate leakage current of 2.15 × 10^(-7) mA/mm and a breakdown voltage of 1180 V. Furthermore, the MIS HEMT displayed exceptional operational stability during dynamic tests, with dynamic resistance remaining only 1.39 times even under 400 V stress.

Research on quantum well intermixing of 680 nm AlGaInP/GaInP semiconductor lasers induced by composited Si-Si_(3)N_(4) dielectric layer

The optical catastrophic damage that usually occurs at the cavity surface of semiconductor lasers has become the main bottleneck affecting the improvement of laser output power and long-term reliability.To improve the output power of 680 nm AlGaInP/GaInP quantum well red semiconductor lasers,Si-Si_(3)N_(4)composited dielectric layers are used to induce its quantum wells to be intermixed at the cavity surface to make a non-absorption window.Si with a thickness of 100 nm and Si_(3)N_(4)with a thickness of 100 nm were grown on the surface of the epitaxial wafer by magnetron sputtering and PECVD as diffusion source and driving source,respectively.Compared with traditional Si impurity induced quantum well intermixing,this paper realizes the blue shift of 54.8 nm in the nonabsorbent window region at a lower annealing temperature of 600 ℃ and annealing time of 10 min.Under this annealing condition,the wavelength of the gain luminescence region basically does not shift to short wavelength,and the surface morphology of the whole epitaxial wafer remains fine after annealing.The application of this process condition can reduce the difficulty of production and save cost,which provides an effective method for upcoming fabrication.

A novel power UMOSFET with a variable K dielectric layer

A novel split-gate power UMOSFET with a variable K dielectric layer is proposed. This device shows a 36.2% reduction in the specific on=state resistance at a breakdown voltage of 115 V, as compared with the SGE-UMOS device. Numerical simulation results indicate that the proposed device features high performance with an improved figure of merit of Qg × RON and BV^2/RON, as compared with the previous power UMOSFET.

Selective synthesis of three-dimensional ZnO@Ag/SiO2@Ag nanorod arrays as surface-enhanced Raman scattering substrates with tunable interior dielectric layer

We describe the synthesis of three-dimensional(3D) multilayer ZnO@Ag/SiO2@Ag nanorod arrays by the physico–chemical method. The surface-enhanced Raman scattering(SERS) performance of the 3D multilayer Zn O@Ag/SiO2@Ag nanorod arrays is studied by varying the thickness of dielectric layer SiO2 and outer-layer noble Ag. The 3D Zn O@Ag/SiO2@Ag nanorod arrays create a huge number of SERS "hot spots" that mainly contribute to the high SERS sensitivity. The great enhancement of SERS results from the electron transfer between ZnO and Ag and different electromagnetic enhancements of Ag nanoparticles(NPs) with different thicknesses. Through the finite-difference time-domain(FDTD) theoretical simulation, the enhancement of SERS signal can be ascribed to a strong electric field enhancement produced in the 3D framework. The simplicity and generality of our method offer great advantages for further understanding the SERS mechanism induced by the surface plasmon resonance(SPR) effect.

Dielectric layer-dependent surface plasmon effect of metallic nanoparticles on silicon substrate

The electromagnetic interaction between Ag nanoparticles on the top of the Si substrate and the incident light has been studied by numerical simulations. It is found that the presence of dielectric layers with different thicknesses leads to the varied resonance wavelength and scattering cross section and consequently the shifted photocurrent response for all wavelengths. These different behaviours are determined by whether the dielectric layer is beyond the domain where the elcetric field of metallic plasmons takes effect, combined with the effect of geometrical optics. It is revealed that for particles of a certain size, an appropriate dielectric thickness is desirable to achieve the best absorption. For a certain thickness of spacer, an appropriate granular size is also desirable. These observations have substantial applications for the optimization of surface plasmon enhanced silicon solar cells.

Positive Bias Temperature Instability Degradation of Buried InGaAs Channel nMOSFETs with InGaP Barrier Layer and Al2O3 Dielectric

Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. Well behaved split C-V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InCaP barrier layer. The direct-current Id-Vg measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive △Vg in the oncurrent region. The Id-Vg degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced aeceptor traps contain both permanent and recoverable traps. Compared with surface channel InCaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.

Anisotropy Characteristics of Magnetostatic Surface Wave Propagating in YIG/Dielectric/Metal Layered Structure

The anisotropy of magnetostatic surface wave （MSSW） propagating in finite width YIG /dielectric/metal layered structure is analyzed. This problem is solved by finding the rigorous solution of each layer from Maxwell equation and the appropriate transmission Green＇s function matrix G. From the relationship of Green＇s function matrixes of dielectric layer and ferrite layer, the dispersion equation is obtained. The MSSW filter is designed to verify the dispersion characteristics. The experiment results are in good agreement with the calculating data from the model.

Polyethylene interfacial dielectric layer for organic semiconductor single crystal based field-effect transistors

Organic semiconductor single crystals(OSSCs) have shown their promising potential in high-performance organic field-effect transistors(OFETs). The interfacial dielectric layers are critical in these OFETs as they not only govern the key semiconductor/dielectric interface quality but also determine the growth of OSSCs by their wetting properties. However, reported interfacial dielectric layers either need rigorous preparation processes, rely on certain surface chemistry reactions, or exhibit poor solvent resistance, which limits their applications in low-cost, large-area, monolithic fabrication of OSSC-based OFETs. In this work, polyethylene(PE) thin films and lamellar single crystals are utilized as the interfacial dielectric layers, providing solvent resistive but wettable surfaces that facilitate the crystallization of 6,13-bis(tri-isopropylsilylethynyl)pentacene(TIPS-PEN) and 6,13-bis(triisopropylsilylethynyl)-5,7,12,14-tetraazapentacene(TIPS-TAP). As evidenced by the presence of ambipolar behavior in TIPS-PEN single crystals and the high electron mobility(2.3 ± 0.34 cm^(2)V^(-1)s^(-1)) in TIPS-TAP single crystals, a general improvement on electron transport with PE interfacial dielectric layers is revealed, which likely associates with the chemically inertness of the saturated C-H bonds. With the advantages in both processing and device operation, the PE interfacial dielectric layer potentially offers a monolithic way for the enhancement of electron transport in solution-processed OSSC-based OFETs.

Improved Performance of Organic Thin Film Transistor with an Inorganic Oxide/Polymer Double-Layer Insulator

We employ the Ta2Os/PVP （poly-4-vinylphenol） double-layer gate insulator to improve the performance of pentacene thin-film transistors. It is found that the double-layer insulator has low leakage current, smooth surface and considerably high capacitance. Compared to Ta205 insulator layers, the device with the Ta2Os/PVP doublelayer insulator exhibits an enhancement of the field-effect mobility from 0.21 to 0.54 cm2/Vs, and the decreasing threshold voltage from 4.38 V to -2.5 V. The results suggest that the Ta2Os/PVP double-layer insulator is a potential gate insulator for fabricating OTFTs with good electrical performance.

Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates

Based on the theoretical and experimental investigation of a thin silicon layer（TSL） with linear variable doping（LVD） and further research on the TSL LVD with a multiple step field plate（MSFP）,a breakdown voltage（BV） model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator（SOI） device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field（ENDIF）,from which the reduced surface field（RESURF） condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection（HVI） line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET（nLDMOS） with MSFP is realized.The experimental breakdown voltage（BV） and specific on-resistance（R on,sp） of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively.

Effective dielectric constant model of electromagnetic backscattering from stratified air–sea surface film–sea water medium

Studies of surface film medium on the sea surface are carried out in this paper for developing the technology to automatically detect and classify sea surface films, and an effective dielectric constant model of electromagnetic backscattering from a stratified air–ocean interface. Numerical results of the new model show the characteristics of effective dielectric constants for the air–sea surface film–sea water medium as follows. The effective dielectric constants decrease with increasing relative dielectric constants of the sea surface films. The effective dielectric constants decrease in horizontal polarization（abbr. HH polarization） and increase in VV vertical polarization（abbr. VV polarization） with increasing radar incident angle. Effective dielectric constants vary with relative sea surface film thickness as a cosinusoidal function of sea surface film thickness. Effective dielectric constant of VV polarization is larger than that of HH polarization. Two potential applications are found with our model, i.e., the retrieval of dielectric constants from the sea surface film, and the film thickness retrieval with our model. Our model has a highly significant influence on improving the technology related to the remote sensing of sea surface films.

Impact of low/high-κ spacer-source overlap on characteristics of tunnel dielectric based tunnel field-effect transistor

The effects of low-κ and high-κ spacer were investigated on the novel tunnel dielectric based tunnel field-effect transistor(TD-FET) mainly based upon ultra-thin dielectric direct tunneling mechanism. Drive currents consist of direct tunneling current and band-to-band tunneling(BTBT) current. Meanwhile, tunneling position of the TD-FET differs from conventional tunnel-FET in which the electron and hole tunneling occur at intermediate rather than surface in channel(or source-channel junction under gate dielectric). The 2-D nature of TD-FET current flow is also discussed that the on-current is degraded with an increase in the spacer width. BTBT current will not begin to play part in tunneling current until gate voltage is 0.2 V. We clearly identify the influence of the tunneling dielectric layer and spacer electrostatic field on the device characteristics by numerical simulations. The inserted Si_3N_4 tunnel layer between P+ region and N+ region can significantly shorten the direct and band-to-band tunneling path, so a reduced subthreshold slope(Ss) and a high on-current can be achieved. Above all the ambipolar current is effectively suppressed, thus reducing off-current. TD-FET demonstrates excellent performance for low-power applications.

Recent progress in flexible capacitive sensors:Structures and properties

The future intelligent era that will be brought about by 5G technology can be well predicted.For example,the connection between humans and smart wearable devices will become increasingly more intimate.Flexible wearable pressure sensors have received much attention as a part of this process.Nevertheless,there is a lack of complete and detailed discussion on the recent research status of capacitive pressure sensors composed of polymer composites.Therefore,this article will mainly discuss the key concepts,preparation methods and main performance of flexible wearable capacitive sensors.The concept of a processing“toolbox”is used to review the developmental status of the dielectric layer as revealed in highly cited literature from the past five years.The preparation methods are categorized into types of processing:primary and secondary.Using these categories,the preparation methods and structure of the dielectric layer are discussed.Their influence on the final capacitive sensing behavior is also addressed.Recent developments in the electrode layer are also systematically reviewed.Finally,the results of the above discussion are summarized and future development trends are discussed.

Self-Assembled Porous-Reinforcement Microstructure-Based Flexible Triboelectric Patch for Remote Healthcare

Realizing real-time monitoring of physiological signals is vital for preventing and treating chronic diseases in elderly individuals. However,wearable sensors with low power consumption and high sensitivity to both weak physiological signals and large mechanical stimuli remain challenges.Here, a flexible triboelectric patch(FTEP) based on porous-reinforcement microstructures for remote health monitoring has been reported. The porousreinforcement microstructure is constructed by the self-assembly of silicone rubber adhering to the porous framework of the PU sponge. The mechanical properties of the FTEP can be regulated by the concentrations of silicone rubber dilution. For pressure sensing, its sensitivity can be effectively improved fivefold compared to the device with a solid dielectric layer, reaching 5.93 kPa^(-1) under a pressure range of 0–5 kPa. In addition, the FTEP has a wide detection range up to 50 kPa with a sensitivity of 0.21 kPa^(-1). The porous microstructure makes the FTEP ultra-sensitive to external pressure, and the reinforcements endow the device with a greater deformation limit in a wide detection range. Finally, a novel concept of the wearable Internet of Healthcare(Io H) system for real-time physiological signal monitoring has been proposed, which could provide real-time physiological information for ambulatory personalized healthcare monitoring.

Dielectric size optimization for high power density in large-scale triboelectric nanogenerators

Triboelectric nanogenerators(TENGs)have emerged as a promising technology to harvest electrical energy from natural motions such as human movement,wind,and water flow.Although TENGs show significant potential in small-scale applications,developing large-scale TENGs capable of generating high power remains a significant challenge.Several factors that can affect the performance of large-scale TENGs are being investigated to overcome this challenge,including the size and configuration of dielectric materials.This study optimizes dielectrics regarding surface area,thickness,and multicell configuration to improve harvested electrical power density in large-scale TENGs.In the studies,glass fiber was used as the positive dielectric,and multipurpose white silicone was used as the negative dielectric because of their high tribo-potential,durability,and easy accessibility.In the size optimization phase,dielectric thicknesses and surface areas that provide the maximum power density were determined.Subsequently,horizontal and vertical multicell configurations were examined to efficiently integrate size-optimized dielectrics.The results reveal that large-scale TENGs with vertical multicell configurations can achieve high and usable energy density for electronics.The findings provide valuable insight into the development of large-scale TENGs with advanced power generation capabilities.

Effects of Hydroxyl Radicals on Introduced Organisms of Ship's Ballast Water Based Micro-Gap Discharge

With the physical method of micro-gap gas discharge, OH. radicals were produced by the ionization of O2 in air and H2O in the gaseous state, in order to explore more effective method totreat the ship＇s ballast water. The surface morphology of Al2O3 dielectric layer was analysed using Atomic Force Microscopy （AFM）, where the size of Al2O3 particles was in the range of 2 μm to 5 μm. At the same time, the biochemical effect of hydroxyl radicals on the introduced organisms and the quality of ship＇s ballast water were studied. The results indicate that the main reasons of cell death are lipid peroxide and damage of the antioxidant enzyme system in Catalase （CAT）, Peroxidase （POD） and Superoxide dismutase （SOD）. In addition, the quality of the ballast water was greatly improved.

A new algorithm for the extraction of the surface waves for the Green's function in layered dielectrics

There exist the complicated waveguide modes as well as the surface waves in the electromagnetic field induced by a horizontal electric dipole in layered lossless dielectrics between two ground planes. In spectral domain, all these modes can be characterized by the rational parts with the real poles of the vector and scalar potentials. The accurate extraction of these modes plays an important role in the evaluation of the Green's function in spatial domain. In this paper, a new algorithm based on rational approximation is presented, which can accurately extract all the real poles and the residues of each pole simultaneously. Thus, we can get all the surface wave modes and waveguide modes, which is of great help to the calculation of the spatial domain Green's function. The numerical results demonstrated the accuracy and efficiency of the proposed method.

Study on the Reflection Spectra of One Dimensional Plasma Photonic Crystals Having Exponentially Graded Materials

The transfer matrix method is used to study the effect of the permittivity profile on the reflectivity of a one dimensional plasma photonic crystal having exponentially graded material. The analysis shows that the proposed structure works as a perfect mirror within a certain frequency range. These frequency ranges can be completely controlled by the permittivity profile of a graded dielectric layer. As expected we observed that these frequency ranges are also controlled by plasma parameters.

Novel high-voltage self-adaptive power device based on interface charge＊

This paper presents a novel high-voltage lateral double diffused metal-oxide semiconductor （LDMOS） with self- adaptive interface charge （SAC） layer and its physical model of the vertical interface electric field. The SAC can be self-adaptive to collect high concentration dynamic inversion holes, which effectively enhance the electric field of dielectric buried layer （EI） and increase breakdown voltage （BV）. The BV and EI of SAC LDMOS increase to 612 V and 600 V/tim from 204 V and 90.7 V/ttm of the conventional silicon-on-insulator, respectively. Moreover, enhancement factors of r/which present the enhanced ability of interface charge on EI are defined and analysed.

Novel high-voltage power lateral MOSFET with adaptive buried electrodes

A new high-voltage and low-specific on-resistance （Ron,sp） adaptive buried electrode （ABE） silicon-on-insulator （SOI） power lateral MOSFET and its analytical model of the electric fields are proposed. The MOSFET features are that the electrodes are in the buried oxide （BOX） layer, the negative drain voltage Vd is divided into many partial voltages and the output to the electrodes is in the buried oxide layer and the potentials on the electrodes change linearly from the drain to the source. Because the interface silicon layer potentials are lower than the neighboring electrode potentials, the electronic potential wells are formed above the electrode regions, and the hole potential wells are formed in the spacing of two neighbouring electrode regions. The interface hole concentration is much higher than tile electron concentration through designing the buried layer electrode potentials. Based on the interface charge enhanced dielectric layer field theory, the electric field strength in the buried layer is enhanced. The vertical electric field EI and the breakdown voltage （BV） of ABE SOI are 545 V/μm and -587 V in the 50 μm long drift region and the 1 μm thick dielectric layer, and a low Ron,sp is obtained. Furthermore, the structure also alleviates the self-heating effect （SHE）. The analytical model matches the simulation results.