A Novel Radiation Tolerant SOI Isolation Structure

A novel radiation tolerant SOI isolation structure,consisting of thin SiO2/polysilicon/field SiO2 multilayers,is proposed. A device with this structure does not show obvious changes in subthreshold characteristics and leakage current,indicating a superior radiation tolerance to traditional LOCOS.

Dependence of R-G Currenton Bulk Traps Characteristics and Silicon Film Structure in SOI Gated-Diode

The dependence of the Recombination- Generation( R- G) current on the bulk trap characteristics and sili- con film structure in SOI lateral p+ p- n+ diode has been analyzed num erically by using the simulation tool,DESSIS- ISE.By varying the bulk trap characteristics such as the trap density and energy level spectrum systematically,the dependence of the R- G current on both of them has been dem onstrated in details.Moreover,the silicon film doping concentration and thickness are changed to make silicon body varies from the fully- depletion m ode into the partial- ly- depletion one.The influence of the transfer of silicon body characteristics on the R- G currenthas also been care- fully examined.A better understanding is obtained of the behavior of bulk trap R- G current in the SOI lateral gat- ed- diode.

A Novel Interface-Gate Structure for SOI Power MOSFET to Reduce Specific On-Resistance

A novel silicon-on-insulator （SOI） power metM-oxide-semiconductor field effect transistor with an interface-gate （IG SOI） structure is proposed, in which the trench polysificon gate extends into the buried oxide layer （BOX） at the source side and an IG is formed. Firstly, the IG offers an extra accumulation channel for the carriers. Secondly, the subsidiary depletion effect of the IG results in a higher impurity doping for the drift region. A low specific on-resistance is therefore obtained under the condition of a slightly enhanced breakdown voltage for the IG SOI. The influences of structure parameters on the device performances are investigated. Compared with the conventional trench gate SOI and lateral planar gate SOI, the specific on-resistances of the IG SOI are reduced by 36.66% and 25.32% with the breakdown voltages enhanced by 2.28% and 10.83% at the same SOI layer of 3 μm, BOX of 1 μm, and half-cell pitch of 5.5 μm, respectively.

FD-SOI器件中PMOS源漏区外延层形貌改善研究

阐述FD-SOI器件中SiGe-RSD形貌不规则是导致Si Cap层被金属扎穿的原因。针对这一问题,对SiGe-RSD的制备工艺进行逐层(L1/L2/L3)优化,最终制备出形貌规则、表面平整的样品。随后的接触通孔工艺环节Si Cap层未被扎穿,形成良好的合金,器件PMOSFET的性能也得到明显提升。

Fabrication and Simulation of Silicon-on-Insulator Structure with Si_3N_4 as a Buried Insulator

In order to minimize the self-heating effect of the classic SOI devices,SOI structures with Si3 N4 film as a buried insulator （SOSN） are successfully formed using epitaxial layer transfer technology for the first time. The new SOI structures are investigated with high-resolution cross-sectional transmission electron microscopy and spreading resistance profile. Experiment results show that the buried Si3 N4 layer is amorphous and the new SOI material has good structural and electrical properties. The output current characteristics and temperature distribution are simulated and compared to those of standard SOI MOSFETs. Furthermore, the channel temperature and negative differential resistance are reduced during high-temperature operation, suggesting that SOSN can effectively mitigate the selfheating penalty. The new SOI device has been verified in two-dimensional device simulation and indicated that the new structures can reduce device self-heating and increase drain current of the SOI MOSFET.

Structured Illumination Chip Based on Integrated Optics

A compact structured illumination chip based on integrated optics is proposed and fabricated on a silicon-on- insulator platform. Based on the simulation of Caussian beam interference, we adopt a chirped diffraction grating to achieve a specific interference pattern. The experimental results match well with the simulations. The portability and flexibility of the structured illumination chip can be increased greatly through horizontal encapsulation. High levels of integration, compared with the conventional structured illumination approach, make this chip very compact, with a footprint of only around 1 mm2. The chip has no optical lenses and can be easily combined with a microfluidic system. These properties would make the chip very suitable for portable 3D scanner and compact super-resolution microscopy applications.

A Soy Protein-Based Composite Film with a Hierarchical Structure Inspired by Nacre

Soy protein-based composite film is a potential replacement for petroleum-based film with multipurpose applica-tions and cleaner production.It is difficult to improve both the tensile strength and toughness of a protein-based film without sacrificing its elongation.In this study,inspired by the hierarchical structure of nacre,a facile yet delicate strategy was developed to fabricate a novel bio-based film with excellent toughness and high strength.Triglycidylamine(TGA)crosslinked soy protein(SPI)as hard phase and thermoplastic polyurethane elastomer(TPU)as soft phase comprise an alternative lay-up hierarchical structure.The interface of these two phases is enhanced using triglycidylamine(TGA)surface-modified TPU(MTPU).The tensile strength of SPI/MTPU/TGA films increases by 392%to 7.78 MPa and their toughness increases by 391%to 8.50 MJ/m^(3) compared to soy protein/glycerol film.The proposed hierarchical structure can also be extended to other high-performance materials and polymers.

Optimization of High EPA Structured Phospholipids Synthesis from （u-3 Fatty Acid Enriched Oil and Soy Lecithin

The molecular structure of phospholipids can be changed enzymatically to obtain different tailor-made phospholipids. Incorporation of ω-3 fatty acids into phospholipids structure increased their oxidative stability, suggesting more health beneficial phospholipids. This study aimed to optimize eicosapentaenoic acid （EPA） incorporation into phospholipids structure by acidolysis reaction using free lipase （EC 3.1.1.3） from Rhizomucor miehei. Deoiled soy lecithin from anjasmoro variety was used as phospholipids source, while ω-3 fatty acid enriched oil was used as acyl source. Oil enriched with ω-3 fatty acids was obtained from low temperature solvent crystallization of lemuru （Sardinella longiceps） by-product. Response surface methodology （RSM） was used in this study to determine the relationship between the three factors （enzyme concentration, reaction time and substrate ratio） and their effects on EPA incorporation into soy lecithin structure. The results showed that the relation between EPA content with three factors （reaction time, enzyme concentration and substrate ratio） was quadratic. The significant factors were substrate ratio and reaction time. Optimum conditions at a ratio of 3.77：1 between ω-3 fatty acids enriched oil and soy lecithin, 30% lipase concentration, and 24.08 h reaction time, gave 22.81% of EPA content of structured phospholipids.

我国肉鸡饲料价格波动特征及影响因素分析

文章旨在分析肉鸡价格波动特征及影响因素,有利于推动禽类养殖业健康稳定发展。基于2002年1月-2022年12月我国252个肉鸡饲料企业样本数据,在通过平稳性检验后,采用VAR模型和方差分解法,从肉鸡饲料价格、供给和需求方面分析引起我国肉鸡饲料价格波动的主要因素。结果显示,在供给层面,肉鸡饲料价格波动的主要影响因素为玉米存量和豆粕存量,第7期玉米存量和豆粕存量对当月肉鸡饲料价格的影响占比分别是30.78%和20.39%。在需求层面,在第7期农村居民人均可支配收入和可繁殖母鸡存栏量对肉鸡饲料价格的影响占比较高,分别为9.06%和6.87%。研究表明,肉鸡饲料价格波动受肉鸡饲料自身价格影响程度最大,随后依次为玉米存量、豆粕存量、农村居民人均可支配收入、可繁殖母鸡存栏量、鱼虾肉价格、肉鸡存栏量、牛肉价格和城镇居民人均可支配收入。

阶梯埋氧型SOI结构的耐压分析

提出了一种阶梯埋氧型SOI(SBOSOI)RESURF器件结构,并解释了该结构的场调制耐压机理,通过2D MEDICI仿真验证了调制机理的正确性.优化了阶梯埋氧阶梯数与耐压的关系,得出阶梯数为3时耐压达到饱和.模拟仿真了比导通电阻和击穿电压,结果表明该结构在埋层厚度为0.2～0.8μm时可使比导通电阻降低40%～50%,耐压提高30%～50%;漂移区厚度小于1μm时比导通电阻降低10%～50%,耐压提高10%～50%.

SOI特种高g值MEMS加速度计设计与分析

基于SOI技术,利用ICP体硅深加工,设计分析了一种新型平面内振动高g值压阻式加速度计。该加速度计包括X轴向与Y轴向单元,采用三梁-扇形质量块平板内振动结构。对称的布局方式,有效的消除了灵敏度的交叉干扰,提高了传感器的测量精度。论文建立了理论模型,并利用ANSYS软件对传感器进行模拟分析与验证,理论与模拟分析结论吻合较好。分析表明,加速度计在X轴向和Y轴向灵敏度分别为1.2μv/g和1.18μv/g;谐振频率分别为479kHz和475kHz。可实现对量程高达25万g加速度的测量。

SOI压阻式压力传感器敏感结构的优化设计

为提高SOI压阻式压力传感器的灵敏度,对传感器敏感结构的弹性膜片和压敏电阻的形状、尺寸等结构参数进行了优化设计。利用COMSOL Multiphysics多物理场耦合分析软件对优化后的敏感结构进行了静力学仿真与分析,完成了敏感芯片的制备和加压测试,测试结果表明:优化后的传感器输出灵敏度为5.98 m V/(V·bar),较原结构输出灵敏度提高了1倍,非线性误差小于0.096%。

耐高温SOI结构压力敏感芯片的研制

如何制作与生产适宜高温环境下应用的压力传感器，一直备受关注。在SIMOX技术SOI晶圆的基础上，设计了压力敏感芯片结构，并基于MEMS工艺制作了芯片。电桥采用1mA恒流源供电，在300℃下，满量程输出≥180mV，灵敏度为30-40mV/（mA.MPa），非线性≤1‰FS，重复性≤1‰FS。与常温测试结果相比，300℃高温下，敏感芯片的静态性能没有明显差异。

大量程SOI压阻式压力传感器设计

文中设计了一种浅凸台结构的SOI压阻式压力传感器。这种膜片结构解决了由于压力量程扩展导致传感器的灵敏度和线性度无法同时满足使用要求的问题。考虑电阻的设计约束以及浅凸台制作过程中的光刻和刻蚀偏差,采用U型电阻保持高灵敏度和线性度。利用ANSYS软件模拟了膜片结构的力学性能,验证了理论分析的正确性;仿真优化了电阻的形状和位置,预估了传感器的性能。介绍了敏感单元的加工工艺。设计的传感器灵敏度为93.4μV/(V·k Pa),非线性误差小于0.22%,可实现对量程高达10 MPa压力的测量。

基于SOI晶圆材料的硅微压传感器

为解决硅微压传感器制作过程中存在的问题,以SOI晶圆材料为基础,使用有限元方法优化设计岛-膜型1kPa压力敏感结构,采用MEMS工艺完成传感器芯片制作,并对封装后的传感器进行了测试。测试结果表明,传感器输出灵敏度大于60 mV/kPa,非线性小于0.1%FS,精度小于0.5%FS,器件具有较好的性能指标。

DRT MC SOI LIGBT器件漂移区新结构的可实现性

简介了减薄漂移区多沟道SOILIGBT结构雏形,根据先进VLSI工艺调研结果讨论了减薄漂移区新型微结构的可实现性,提出了可能实现的三种表面微结构及其工艺实现方法;指出了这种器件雏形结构存在的几个主要问题,有针对性地探讨了改进措施,并提出了面向智能PowerICs应用的同心圆环源漏互包SOILIGBT结构,及其迄待研究的主要问题与部分解决措施。

基于SOI材料的兵器微电子技术应用分析

随着集成技术进入亚微米阶段,传统的硅基集成电路由于存在闩锁等不利因素,使其应用受到了限制。而基于SOI材料的微电子技术是能突破硅材料与硅集成电路限制的新技术,是国际半导体的前沿技术之一,是发展兵器装备用元器件的又一关键材料技术。介绍了SOI材料结构技术用于微电子器件的优势、SOI结构及基于SOI结构材料的兵器微电子技术应用,展望了SOI技术的发展前景。

漂移区减薄的多沟道薄膜SOILIGBT的研究(Ⅰ)——低压截止态泄漏电流的温度特性

提出了一种新结构薄膜 SOI L IGBT——漂移区减薄的多沟道薄膜 SOI LIGBT( DRT-MC TFSOI L IGB)。主要研究了其低压截止态泄漏电流在 4 2 3～ 573K范围的温度特性。指出 ,通过合理的设计可以使该种新器件具有很低的截止态高温泄漏电流 ,很高的截止态击穿电压 ,足够大的正向导通电流和足够低的正向导通压降。还指出 ,它不仅适用于高温低压应用 ,而且适用于高温高压应用。

实现高温工作的SOI器件埋层结构研究

硅基集成电路不能胜任高温工作环境,其高温工作上限一般为125℃。而基于SOI材料及其结构的器件,能突破高温的限制。介绍了SOI材料结构技术用于高温电路的优势,分析了影响高温性能的自加热效应。为实现良好的高温性能,比较了几种不同的埋层结构,提出了沟道下用氮化铝作埋层的SOI器件新结构,并对其高温输出性能随温度的变化进行了研究分析,得出了具有指导意义的分析结果。同时提出了根据埋层材料的介电常数不同,进行等效电容折算埋层厚度的新观点,从另一层面提出了抑制自加热效应的理论依据。

基于全耗尽技术的SOI CMOS集成电路研究

介绍了电路的工作原理,对主要的延迟和选通控制单元及整体电路进行了模拟仿真,证明电路逻辑功能达到设计要求。根据电路的性能特点,采用绝缘体上硅结构,选用薄膜全耗尽SOICMOS工艺进行试制。测试结果表明:与同类体硅电路相比,工作频率提高三倍,静态功耗仅为体硅电路的10%,且电路的101级环振总延迟时间也仅为体硅电路的20%,实现了电路对高速低功耗的要求。