A novel SiC high-k superjunction power MOSFET integrated Schottky barrier diode with improved forward and reverse performance

A new SiC superjunction power MOSFET device using high-k insulator and p-type pillar with an integrated Schottky barrier diode(Hk-SJ-SBD MOSFET)is proposed,and has been compared with the SiC high-k MOSFET(Hk MOSFET),SiC superjuction MOSFET(SJ MOSFET)and the conventional SiC MOSFET in this article.In the proposed SiC Hk-SJ-SBD MOSFET,under the combined action of the p-type region and the Hk dielectric layer in the drift region,the concentration of the N-drift region and the current spreading layer can be increased to achieve an ultra-low specific on-resistance(Ron,sp).The integrated Schottky barrier diode(SBD)also greatly improves the reverse recovery performance of the device.TCAD simulation results indicate that the Ron,sp of the proposed SiC Hk-SJ-SBD MOSFET is 0.67 mΩ·cm^(2)with a 2240 V breakdown voltage(BV),which is more than 72.4%,23%,5.6%lower than that of the conventional SiC MOSFET,Hk SiC MOSFET and SJ SiC MOSFET with the 1950,2220,and 2220V BV,respectively.The reverse recovery time and reverse recovery charge of the proposed MOSFET is 16 ns and18 nC,which are greatly reduced by more than 74%and 94%in comparison with those of all the conventional SiC MOSFET,Hk SiC MOSFET and SJ SiC MOSFET,due to the integrated SBD in the proposed MOSFET.And the trade-off relationship between the Ron,sp and the BV is also significantly improved compared with that of the conventional MOSFET,Hk MOSFET and SJ MOSFET as well as the MOSFETs in other previous literature,respectively.In addition,compared with conventional SJ SiC MOSFET,the proposed SiC MOSFET has better immunity to charge imbalance,which may bring great application prospects.

Investigation of degradation and recovery characteristics of NBTI in 28-nm high-k metal gate process

Degradation induced by the negative bias temperature instability(NBTI)can be attributed to three mutually uncoupled physical mechanisms,i.e.,the generation of interface traps(ΔV_(IT)),hole trapping in pre-existing gate oxide defects(ΔV_(HT)),and the generation of gate oxide defects(ΔV_(OT)).In this work,the characteristic of NBTI for p-type MOSFET fabricated by using a 28-nm high-k metal gate(HKMG)process is thoroughly studied.The experimental results show that the degradation is enhanced at a larger stress bias and higher temperature.The effects of the three underlying subcomponents are evaluated by using the comprehensive models.It is found that the generation of interface traps dominates the NBTI degradation during long-time NBTI stress.Moreover,the NBTI parameters of the power-law time exponent and temperature activation energy as well as the gate oxide field acceleration are extracted.The dependence of operating lifetime on stress bias and temperature is also discussed.It is observed that NBTI lifetime significantly decreases as the stress increases.Furthermore,the decrease of charges related to interface traps and hole detrapping in pre-existing gate oxide defects are used to explain the recovery mechanism after stress.

High-k材料研究进展与存在的问题

随着集成电路的飞速发展,SiO2作为传统的栅介质将不能满足MOSFET器件高集成度的要求,需要一种新型High-k材料来代替传统的SiO2,这就要综合考虑以下几个方面问题:(1)介电常数和势垒高度;(2)热稳定性;(3)薄膜形态;(4)界面质量;(5)与Si基栅兼容;(6)工艺兼容性;(7)可靠性。本文综述了几类High-k栅介质材料的研究现状及存在的问题。目前任何一种有望替代SiO2的栅介质材料都不能完全满足上述几点要求。但是,科学工作者们已经发现了几种有希望的High-k候选材料。

TiO_2/Al_2O_3堆栈结构high-k薄膜的制备及性能

采用磁控溅射法制备了TiO_2/Al_2O_3堆栈结构高k栅介质薄膜,研究了不同后处理条件对等效氧化物厚度,界面电荷和界面扩散的影响。实验结果表明:400℃退火后,TiO_2已经结晶,退火可以降低漏电流密度和介电层中的电荷密度。同时,退火使Ti进一步向Al_2O3层扩散,形成TiO_2和Al_2O_3的混合层,Al_2O_3层过薄时不能有效阻挡TiO_2的扩散。

High-k材料MOS器件的PISCES-II模拟

High-k材料是指介电常数k高于SiO2的材料。使用high-k材料做栅绝缘层,是减小MOS器件栅绝缘层直接隧道击穿(DirectTunneling,DT)电流的有效方法。文章在二维器件模拟软件PISCES-II中添加了模拟以high-k材料为栅绝缘层的MOS器件模型,并对SiO2和high-k材料的MOS晶体管器件特性进行了模拟比较,成功地验证了所加high-k材料MOS器件模型的正确性。改进后的PISCES-II程序,可以方便地对以各种high-k材料为栅绝缘层的器件性能进行模拟。

A Frequency-Independent Equivalent Circuit for High-k Stacked Monolithic Transformers

A new 2-Π lumped element equivalent circuit model for high-k stacked on-chip transformers is proposed. The model parameters are extracted with high precision, mainly based on analytical methods. The developed model enables fast and accurate time domain transient analysis and noise analysis in RFIC simulation since all elements in the model are fre- quency independent. The validity of the proposed model has been demonstrated by a fabricated monolithic stacked trans- former in TSMC＇s 0.13μm mixed-signal （MS）/RF CMOS＇ process.

Key technologies for dual high-k and dual metal gate integration

The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiOx. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1（NH4OH：H2O2：H2O = 1 ： 1 ： 5） and DHF-based solution for the selective removing of n MOS TaN and Hf Si ON and by BCl3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON.After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl3/SF6/O2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.

Petrogenesis of the Langdu High-K Calc-Alkaline Intrusions in Yunnan Province: Constraints from Geochemistry and Sr-Nd Isotopes

The Langdu high-K calc-alkaline intrusions are located in the Zhongdian area, which is the southern part of the Yidun island arc. These intrusive rocks consist mainly of monzonite porphyry, granodiorite, and diorite porphyry. The K20 content of majority of these rocks is greater than 3%, and, in the K20-SiO2 diagram, all the samples fall into the high-K calc-alkaline to shoshonitic fields. They are enriched in light rare earth elements （LREEs） and depleted in heavy rare earth elements （HREEs; LaN/YbN = 14.3-21.2）, and show slightly negative Eu anomalies （6Eu = 0.77-1.00）. These rocks have high K, Rb, Sr, and Ba contents; moderate to high enrichment of compatible elements （Cr = 36.7-79.9 ppm, Co = 9.6-16.4 ppm, and MgO = 2.2%-3.4%）; low Nb, Ta, and Ti contents, and characteristic of low high field strength elements（HFSEs） versus incompatible elements ratios （Nb/Th = 0.75, Nb/La = 0.34） and incompatible elements ratios （Nb/U = 3.0 and Ce/Pb = 5.1, Ba/Rb = 12.0）. These rocks exhibit restricted Sr and Nd isotopic compositions, with （87Sr/S6Sr）i values ranging from 0.7044 to 0.7069 and ENd（t） values from -2.8 to -2.2. The Sr-Nd isotope systematic and specific trace element ratios suggest that Langdu high-K calc-alkaline intrusive rocks derived from a metasomatized mantle source. The unique geochemical feature of intrusive rocks can be modeled successfully using different members of a slightly enriched mantle, a slab-derived fluid, and terrigenous sediments. It can be inferred that the degree of partial melting and the presence of specific components are temporally related to the tectonic evolution of the Zhongdian island arc. Formation of these rocks can be explained by the various degrees of melting within an ascending region of the slightly enriched mantle, triggered by the subduction of the Garz^--Litang ocean, and an interaction between the slab-derived fluid and the terrigenous sediments.

Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars

This paper presents a new silicon-on-insulator(SOI) lateral-double-diffused metal-oxide-semiconductor transistor(LDMOST) device with alternated high-k dielectric and step doped silicon pillars(HKSD device). Due to the modulation of step doping technology and high-k dielectric on the electric field and doped profile of each zone, the HKSD device shows a greater performance. The analytical models of the potential, electric field, optimal breakdown voltage, and optimal doped profile are derived. The analytical results and the simulated results are basically consistent, which confirms the proposed model suitable for the HKSD device. The potential and electric field modulation mechanism are investigated based on the simulation and analytical models. Furthermore, the influence of the parameters on the breakdown voltage(BV) and specific on-resistance(R_(on,sp)) are obtained. The results indicate that the HKSD device has a higher BV and lower R_(on,sp) compared to the SD device and HK device.

Fabrication and characteristics of high-K HfO2 gate dielectrics on n-germanium

This paper reports that the high-K HfO2 gate dielectrics are fabricated on n-germanium substrates by sputtering Hf on Ge and following by a furnace annealing. The impacts of sputtering ambient, annealing ambient and annealing temperature on the electrical properties of high-K HfO2 gate dielectrics on germanium substrates are investigated. Experimental results indicate that high-K HfO2 gate dielectrics on germanium substrates with good electrical characteristics are obtained, the electrical properties of high-K HfO2 gate dielectrics is strongly correlated with sputtering ambient, annealing ambient and annealing temperature.

High performance trench MOS barrier Schottky diode with high-k gate oxide

A novel trench MOS barrier Schottky diode（TMBS） device with a high-k material introduced into the gate insulator is reported, which is named high-k TMBS. By simulation with Medici, it is found that the high-k TMBS can have 19.8% lower leakage current while maintaining the same breakdown voltage and forward turn-on voltage compared with the conventional regular trench TMBS.

Effect of interface-roughness scattering on mobility degradation in SiGe p-MOSFETs with a high-k dielectric/SiO2 gate stack＊

A physical model for mobility degradation by interface-roughness scattering and Coulomb scattering is proposed for SiGe p-MOSFET with a high-k dielectric/SiO2 gate stack. Impacts of the two kinds of scatterings on mobility degradation are investigated. Effects of interlayer （SiO2） thickness and permittivities of the high-k dielectric and interlayer on carrier mobility are also discussed. It is shown that a smooth interface between high-k dielectric and interlayer, as well as moderate permittivities of high-k dielectrics, is highly desired to improve carriers mobility while keeping alow equivalent oxide thickness. Simulated results agree reasonably with experimental data.

Challenges in Atomic-Scale Characterization of High-k Dielectrics and Metal Gate Electrodes for Advanced CMOS Gate Stacks

The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy （HRTEM） and the related techniques based on scanning transmission electron microscopy （STEM）, including high-angle annular dark- field （HAADF） imaging （also known as Z-contrast imaging）, electron energy-loss spectroscopy （EELS）, and energy dispersive X-ray spectroscopy （EDS）, due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices. In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics. In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed. The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4. Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.

Current Progress of Hf(Zr)-Based High-k Gate Dielectric Thin Films

With the continued downscaling of complementary metal-oxide-semiconductor field effect transistor dimensions, high-dielectric constant （high-k） gate materials, as alternatives to SiO2, have been extensively investigated. Hf （Zr）-based high-k gate dielectric thin films have been regarded as the most promising candidates for high-k gate dielectric according to the International Technology Roadmap for Semiconductor due to their excellent physical properties and performance. This paper reviews the recent progress on Hf （Zr）-based high-k gate dielectrics based on PVD （physical vapor deposition） process. This article begins with a survey of various methods developed for generating Hf （Zr）-based high-k gate dielectrics, and then mainly focuses on microstructure, synthesis, characterization, formation mechanisms of interfacial layer, and optical properties of Hf （Zr）-based high-k gate dielectrics. Finally, this review concludes with personal perspectives towards future research on Hf （Zr）-based high-k gate dielectrics.

A two-dimensional threshold voltage analytical model for metal-gate/high-k/SiO_2 /Si stacked MOSFETs

In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson＇s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson＇s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.

Improved performance of back-gate MoS2 transistors by NH3-plasma treating high-k gate dielectrics

NH3-plasma treatment is used to improve the quality of the gate dielectric and interface. Al2O3 is adopted as a buffer layer between HfO2 and MoS2 to decrease the interface-state density. Four groups of MOS capacitors and back-gate transistors with different gate dielectrics are fabricated and their C–V and I–V characteristics are compared. It is found that the Al2O3/HfO2 back-gate transistor with NH3-plasma treatment shows the best electrical performance: high on–off current ratio of 1.53 × 107, higher field-effect mobility of 26.51 cm2/V·s, and lower subthreshold swing of 145 m V/dec.These are attributed to the improvements of the gate dielectric and interface qualities by the NH3-plasma treatment and the addition of Al2O3 as a buffer layer.

Improvement of the high-k/Ge interface thermal stability using an in-situ ozone treatment characterized by conductive atomic force microscopy

In this work, an in-situ ozone treatment is carried out to improve the interface thermal stability of HfO_2/Al_2O_3 gate stack on germanium（Ge） substrate. The micrometer scale level of HfO_2/Al_2O_3 gate stack on Ge is studied using conductive atomic force microscopy（AFM） with a conductive tip. The initial results indicate that comparing with a non insitu ozone treated sample, the interface thermal stability of the sample with an in-situ ozone treatment can be substantially improved after annealing. As a result, void-free surface, low conductive spots, low leakage current density, and relative high breakdown voltage high-κ/Ge are obtained. A detailed analysis is performed to confirm the origins of the changes.All results indicate that in-situ ozone treatment is a promising method to improve the interface properties of Ge-based three-dimensional（3D） devices in future technology nodes.

Temperature- and voltage-dependent trap generation model in high-k metal gate MOS device with percolation simulation

High-k metal gate stacks are being used to suppress the gate leakage due to tunneling for sub-45 nm technology nodes.The reliability of thin dielectric films becomes a limitation to device manufacturing,especially to the breakdown characteristic.In this work,a breakdown simulator based on a percolation model and the kinetic Monte Carlo method is set up,and the intrinsic relation between time to breakdown and trap generation rate R is studied by TDDB simulation.It is found that all degradation factors,such as trap generation rate time exponent m,Weibull slope β and percolation factor s,each could be expressed as a function of trap density time exponent α.Based on the percolation relation and power law lifetime projection,a temperature related trap generation model is proposed.The validity of this model is confirmed by comparing with experiment results.For other device and material conditions,the percolation relation provides a new way to study the relationship between trap generation and lifetime projection.

Analysis of flatband voltage shift of metal/high-k/SiO_2/Si stack based on energy band alignment of entire gate stack

A theoretical model of flatband voltage （VFB） of metal/high-k/Si02/Si stack is proposed based on band alignment of entire gate stack, i.e., the VFB is obtained by simultaneously considering band alignments of metal/high-k, high-k/SiO2 and SiO2/Si interfaces, and their interactions. Then the VFB of TiN/HfO2/SiO2/Si stack is experimentally obtained and theoretically investigated by this model. The theoretical calculations are in good agreement with the experimental results. Furthermore, both positive VFB shift of TiN/HfO2/SiO2/Si stack and Fermi level pinning are successfully interpreted and attributed to the dielectric contact induced gap states at TiN/HfO2 and HfO2/SiO2 interfaces.

Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high-k metal gate NMOSFET with kMC TDDB simulations

The thickness effect of the TiN capping layer on the time dependent dielectric breakdown（TDDB） characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper.Based on experimental results,it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer.From the charge pumping measurement and secondary ion mass spectroscopy（SIMS） analysis,it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density.In addition,the influences of interface and bulk trap density ratio Nit/Not are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo（kMC） method.The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses.