An Improved Power Efficient Clock Pulsed D Flip-flop Using Transmission Gate

Recent digital applications will require highly efficient and high-speed gadgets and it is related to the minimum delay and power consumption.The proposed work deals with a low-power clock pulsed data flip-flop(D flip-flop)using a transmission gate.To accomplish a power-efficient pulsed D flip-flop,clock gating is proposed.The gated clock reduces the unnecessary switching of the transistors in the circuit and thus reduces the dynamic power consumption.The clock gating approach is employed by using an AND gate to disrupt the clock input to the circuit as per the control signal called Enable.Due to this process,the clock gets turned off to reduce power consumption when there is no change in the output.The proposed transmission gate-based pulsed D flip-flop’s performance with clock gating and without clock gating circuit is analyzed.The proposed pulsed D flip-flop power consumption is 1.586μw less than the without clock gated flip-flop.Also,the authors have designed a 3-bit serial-in and parallel-out shift register using the proposed D flip-flop and analyzed the performance.Tanner Electronic Design Automation tool is used to simulate all the circuits with 45 nm technology.

主从型D触发器中短路功耗的研究

在对主从型D触发器分析短路功耗的基础上,本文提出了一种使D触发器工作在两个有一定相位差的时钟下以减少D触发器短路功耗的方法.模拟结果证明了该方法的有效性.

Design of an 8 bit differential paired eFuse OTP memory IP reducing sensing resistance

For the conventional single-ended eFuse cell, sensing failures can occur due to a variation of a post-program eFuse resistance during the data retention time and a relatively high program resistance of several kilo ohms. A differential paired eFuse cell is designed which is about half the size smaller in sensing resistance of a programmed eFuse link than the conventional single-ended eFuse cell. Also, a sensing circuit of sense amplifier is proposed, based on D flip-flop structure to implement a simple sensing circuit. Furthermore, a sensing margin test circuit is proposed with variable pull-up loads out of consideration for resistance variation of a programmed eFuse. When an 8 bit eFuse OTP IP is designed with 0.18 ~tm standard CMOS logic of TSMC, the layout dimensions are 229.04 μm ×100.15μm. All the chips function successfully when 20 test chips are tested with a program voltage of 4.2 V.

Reversible Logic Based MOS Current Mode Logic Implementation in Digital Circuits

Now a days,MOS Current Mode Logic(MCML)has emerged as a better alternative to Complementary Metal Oxide Semiconductor(CMOS)logic in digital circuits.Recent works have only traditional logic gates that have issues with information loss.Reversible logic is incorporated with MOS Current Mode Logic(MCML)in this proposed work to solve this problem,which is used for multiplier design,D Flip-Flop(DFF)and register.The minimization of power and area is the main aim of the work.In reversible logic,the count of outputs and inputs is retained as the same value for creating one-to-one mapping.A unique output vector set can be generated for each input vector set and information loss is also prevented.In reversible MCML based multiplier,reversible logic full adder is utilized to minimize the area and power.D flip-flops based on reversible MCML are often designed to store information that is then combined to form a reversible MCML based register.The proposed reversible MCML multiplier attains average power of 0.683 mW,Reversible MCML based DFF achieves 0.56μW and Reversible MCML based 8-bit register attains 04.04μW.The result shows that the proposed Reversible MCML based multiplier,Reversible MCML based D flip-flop and ReversibleMCML based register achieves better performance in terms of current,power dissipation,average power and area.

Design of ternary D flip-flop with pre-set and pre-reset functions based on resonant tunneling diode literal circuit

The problems existing in the binary logic system and the advantages of multiple-valued logic (MVL) are introduced. A literal circuit with three-track-output structure is created based on resonant tunneling diodes (RTDs) and it has the most basic memory function. A ternary RTD D flip-flop with pre-set and pre-reset functions is also designed, the key module of which is the RTD literal circuit. Two types of output structure of the ternary RTD D flip-flop are optional: one is three-track and the other is single-track; these two structures can be transformed conveniently by merely adding tri-valued RTD NAND, NOR, and inverter units after the three-track output. The design is verified by simulation. Ternary flip-flop consists of an RTD literal circuit and it not only is easy to understand and implement but also provides a solution for the algebraic interface between the multiple-valued logic and the binary logic. The method can also be used for design of other types of multiple-valued RTD flip-flop circuits.

Monolithically integrated enhancement/depletion-mode AlGaN/GaN HEMT D flip-flop using fluorine plasma treatment

Depletion-mode and enhancement-mode AlGaN/GaN HEMTs using fluorine plasma treatment were integrated on one wafer.Direct-coupled FET logic circuits,such as an E/D HEMT inverter,NAND gate and D flip-flop,were fabricated on an AlGaN/GaN heterostructure.The D flip-flop and NAND gate are demonstrated in a GaN system for the first time.The dual-gate AlGaN/GaN E-HEMT substitutes two single-gate E-HEMTs for simplifying the NAND gate and shrinking the area,integrating with a conventional AlGaN/GaN D-HEMT and demonstrating a NAND gate.E/D-mode D flip-flop was fabricated by integrating the inverters and the NAND gate on the AlGaN/GaN heterostructure.At a supply voltage of 2 V,the E/D inverter shows an output logic swing of 1.7 V,a logic-low noise margin of 0.49 V and a logic-high noise margin of 0.83 V.The NAND gate and D flip-flop showed correct logic function demonstrating promising potential for GaN-based digital ICs.

Security Enhancement of Arbiter-Based Physical Unclonable Function on FPGA

In order to reduce physical unclonable fixnction （PUF） response instability and imbalance caused by the metastability and the bias of arbiter, this paper uses an improved balanced D flip-plop （DFF） based on the unbalanced DFF to reduce the bias in response output and enhances the security of PUF by adopting two balanced DFFs in series. The experimental results show that two cascaded balanced DFFs improve the stability of the DFF, and the output of two balanced DFFs is more reliable. The entropy of output is fixed at 98.7%.

All-optical pseudo noise sequence generator using a micro-ring resonator

A scheme for the generation of a pseudo noise(PN)sequence in the optical domain is proposed.The cascaded units of micro-ring resonator(MRR)-based D flip-flop are used to design the device.D flip-flops consist of a single MRR and share the same optical pump signal.Numerical analysis is performed,and simulated results are discussed.The proposed device can be used as a building block for optical computing and for creating an information processing system.