A hardware-software co-simulation method for system on chip (SOC) design is discussed. It is based on an instruction set simulator (ISS) and an event-driven hardware simulator, and a bus interface model that is descri...A hardware-software co-simulation method for system on chip (SOC) design is discussed. It is based on an instruction set simulator (ISS) and an event-driven hardware simulator, and a bus interface model that is described in C language provides the interface between the two. The bus interface model and the ISS are linked into a singleton program--the software simulator, which communicate with the hardware simulator through Windows sockets. The implementation of the bus interface model and the synchronization between hardware and software simulator are discussed in detail. Co-simulation control of the hardware simulator is also discussed.展开更多
A series of 2D direct numerical simulations were performed with an accurate level set method for single drop impacts.The adopted ACLS method was validated to be efficient with perfect mass conservation in both normal ...A series of 2D direct numerical simulations were performed with an accurate level set method for single drop impacts.The adopted ACLS method was validated to be efficient with perfect mass conservation in both normal and oblique impacts.A square-root correction for neck bases was modified in accuracy as well as scope of applications.In addition,process of jet formation and evolution was studied to reveal internal dynamics in drop impacts.It's found that pressure gradient and vortex are coexisting and completive reasons for jet topology while the inclined angle has a significant effect on them.Mechanisms of jet formation and evolution are different in the front and back necks.With the help of PDF distribution and correction calculation,a compromise in the competition is observed.This work lays a solid foundation for further studies of dynamics in gas-liquid flows.展开更多
Hydration process, crack potential and setting time of concrete grade C30, C40 and C50 were monitored by using a non-contact electrical resistivity apparatus, a novel plastic ring mould and penetration resistance meth...Hydration process, crack potential and setting time of concrete grade C30, C40 and C50 were monitored by using a non-contact electrical resistivity apparatus, a novel plastic ring mould and penetration resistance methods, respectively. The results show the highest resistivity of C30 at the early stage until a point when C50 accelerated and overtook the others. It has been experimentally confirmed that the crossing point of C30 and C50 corresponds to the final setting time of C50. From resistivity derivative curve, four different stages were observed upon which the hydration process is classified; these are dissolution, induction, acceleration and deceleration periods. Consequently, restrained shrinkage crack and setting time results demonstrated that C50 set and cracked the earliest. The cracking time of all the samples occurred within a reasonable experimental period thus the novel plastic ring is a convenient method for predicting concrete＇s crack potential. The highest inflection time（t_i） obtained from resistivity curve and the final setting time（t_f） were used with crack time（t_c） in coming up with mathematical models for the prediction of concrete＇s cracking age for the range of concrete grade considered. Finally, an ANSYS numerical simulation supports the experimental findings in terms of the earliest crack age of C50 and the crack location.展开更多
Instruction Set Simulator （ISS） is a highly abstracted and executable model of micro architecture. It is widely used in the fields of verification and debugging during the development of microprocessors. However, wi...Instruction Set Simulator （ISS） is a highly abstracted and executable model of micro architecture. It is widely used in the fields of verification and debugging during the development of microprocessors. However, with the emergence of Chip Multi-Processors, the single-core ISS cannot meet the needs of microprocessor development. In this paper, we introduce our multi-core chip architecture first, after that a general methodology to expand a single-core ISS to a multi- core ISS （MCISS） is proposed. On this basis, a real-time comparison environment is created for multi-core verification, and the problems of multi-core communication and synchronization are addressed gracefully. With the ＂save and restore＂ mechanism, the verification procedure and the debugging are speeding up greatly.展开更多
文摘A hardware-software co-simulation method for system on chip (SOC) design is discussed. It is based on an instruction set simulator (ISS) and an event-driven hardware simulator, and a bus interface model that is described in C language provides the interface between the two. The bus interface model and the ISS are linked into a singleton program--the software simulator, which communicate with the hardware simulator through Windows sockets. The implementation of the bus interface model and the synchronization between hardware and software simulator are discussed in detail. Co-simulation control of the hardware simulator is also discussed.
基金Supported by the National Natural Science Foundation of China(91541202,51276163)
文摘A series of 2D direct numerical simulations were performed with an accurate level set method for single drop impacts.The adopted ACLS method was validated to be efficient with perfect mass conservation in both normal and oblique impacts.A square-root correction for neck bases was modified in accuracy as well as scope of applications.In addition,process of jet formation and evolution was studied to reveal internal dynamics in drop impacts.It's found that pressure gradient and vortex are coexisting and completive reasons for jet topology while the inclined angle has a significant effect on them.Mechanisms of jet formation and evolution are different in the front and back necks.With the help of PDF distribution and correction calculation,a compromise in the competition is observed.This work lays a solid foundation for further studies of dynamics in gas-liquid flows.
基金Funded by National Natural Science Foundation of China(Nos.51478200 and 51178202)
文摘Hydration process, crack potential and setting time of concrete grade C30, C40 and C50 were monitored by using a non-contact electrical resistivity apparatus, a novel plastic ring mould and penetration resistance methods, respectively. The results show the highest resistivity of C30 at the early stage until a point when C50 accelerated and overtook the others. It has been experimentally confirmed that the crossing point of C30 and C50 corresponds to the final setting time of C50. From resistivity derivative curve, four different stages were observed upon which the hydration process is classified; these are dissolution, induction, acceleration and deceleration periods. Consequently, restrained shrinkage crack and setting time results demonstrated that C50 set and cracked the earliest. The cracking time of all the samples occurred within a reasonable experimental period thus the novel plastic ring is a convenient method for predicting concrete＇s crack potential. The highest inflection time（t_i） obtained from resistivity curve and the final setting time（t_f） were used with crack time（t_c） in coming up with mathematical models for the prediction of concrete＇s cracking age for the range of concrete grade considered. Finally, an ANSYS numerical simulation supports the experimental findings in terms of the earliest crack age of C50 and the crack location.
文摘Instruction Set Simulator （ISS） is a highly abstracted and executable model of micro architecture. It is widely used in the fields of verification and debugging during the development of microprocessors. However, with the emergence of Chip Multi-Processors, the single-core ISS cannot meet the needs of microprocessor development. In this paper, we introduce our multi-core chip architecture first, after that a general methodology to expand a single-core ISS to a multi- core ISS （MCISS） is proposed. On this basis, a real-time comparison environment is created for multi-core verification, and the problems of multi-core communication and synchronization are addressed gracefully. With the ＂save and restore＂ mechanism, the verification procedure and the debugging are speeding up greatly.
