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基于∑-△M的五阶MFLR数字微加速度计闭环控制系统 被引量:1
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作者 杜松杰 苑伟政 +1 位作者 陈方 常洪龙 《传感器与微系统》 CSCD 北大核心 2014年第12期120-123,共4页
为了进一步抑制加速度计信号带宽范围内的噪声,提出并设计了一种基于∑-△M的五阶多反馈谐振式(MFLR)微机械加速度计闭环控制系统,该系统通过增加额外的内部负反馈对量化噪声进行再一次整形.微机械加速度计结构为一种全差分式结构,在... 为了进一步抑制加速度计信号带宽范围内的噪声,提出并设计了一种基于∑-△M的五阶多反馈谐振式(MFLR)微机械加速度计闭环控制系统,该系统通过增加额外的内部负反馈对量化噪声进行再一次整形.微机械加速度计结构为一种全差分式结构,在结构层厚度为60 μm、基底层厚度为400μm的SOI硅片上,经过光刻、溅射、深度反应离子刻蚀等工艺步骤加工而成.整个闭环控制系统的Matlab/Simulink模型首先被建立,然后采用“单位圆分析法”进行系统参数的设定,系统仿真显示:当输入幅值1gn、频率128Hz的加速度信号时,加速度计的噪声为-136.2 dB,与传统五阶MF结构的∑-△M闭环控制系统相比,在0 ~500 Hz信号带宽范围内的噪声降低了7.9dB.最后整个系统在四层PCB电路板上进行了功能性验证和测试. 展开更多
关键词 微机械加速度计 SIGMA-DELTA modulator(∑-△M) 闭环控制 高频段噪声
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An ultra-sensitive and easy-to-use assay for sensing human UGT1A1 activities in biological systems 被引量:2
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作者 Ya-Di Zhu Hui-Lin Pang +8 位作者 Qi-Hang Zhou Zi-Fei Qin Qiang Jin Moshe Finel Yi-Nan Wang Wei-Wei Qin Yin Lu Dan-Dan Wang Guang-Bo Ge 《Journal of Pharmaceutical Analysis》 SCIE CAS CSCD 2020年第3期263-270,共8页
The human UDP-glucuronosyltransferase 1A1(UGT1A1),one of the most essential conjugative enzymes,is responsible for the metabolism and detoxification of bilirubin and other endogenous substances,as well as many differe... The human UDP-glucuronosyltransferase 1A1(UGT1A1),one of the most essential conjugative enzymes,is responsible for the metabolism and detoxification of bilirubin and other endogenous substances,as well as many different xenobiotic compounds.Deciphering UGT1A1 relevance to human diseases and characterizing the effects of small molecules on the activities of UGT1A1 requires reliable tools for probing the function of this key enzyme in complex biological matrices.Herein,an easy-to-use assay for highly-selective and sensitive monitoring of UGT1A1 activities in various biological matrices,using liquid chromatography with fluorescence detection(LC-FD),has been developed and validated.The newly developed LC-FD based assay has been confirmed in terms of sensitivity,specificity,precision,quantitative linear range and stability.One of its main advantages is lowering the limits of detection and quantification by about 100-fold in comparison to the previous assay that used the same probe substrate,enabling reliable quantification of lower amounts of active enzyme than any other method.The precision test demonstrated that both intra-and inter-day variations for this assay were less than 5.5%.Furthermore,the newly developed assay has also been successfully used to screen and characterize the regulatory effects of small molecules on the expression level of UGT1A1 in living cells.Ove rall,an easy-to-use LC-FD based assay has been developed for ultra-sensitive UGT1A1 activities measurements in various biological systems,providing an inexpensive and practical approach for exploring the role of UGT1A1 in human diseases,interactions with xenobiotics,and characterization modulatory effects of small molecules on this conjugative enzyme. 展开更多
关键词 UGT1A1 LC-FD N-butyl-4-(4-hydroxyphenyl)-1 8-naphthalimide modulators
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Integration and verification case of IP-core based system on chip design 被引量:3
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作者 胡越黎 周谌 《Journal of Shanghai University(English Edition)》 CAS 2010年第5期349-353,共5页
In this paper, the design and verification process of an automobile-engine-fan control system on chip (SoC) are introduced. The SoC system, SHU-MV08, reuses four new intellectual property (IP) cores and the design... In this paper, the design and verification process of an automobile-engine-fan control system on chip (SoC) are introduced. The SoC system, SHU-MV08, reuses four new intellectual property (IP) cores and the design flow is accomplished with 0.35 btm chartered CMOS technology. Some special functions of IP cores, the detailed integration scheme of four IP cores, and the verification method of the entire SoC are presented. To settle the verification problems brought by analog IP cores, NanoSim based chip-level mixed-signal verification method is introduced. The verification time is greatly reduced and the first tape-out achieves success which proves the validity of our design. 展开更多
关键词 system on chip (SoC) intellectual property (IP)-core integration VERIFICATION pulse width modulation (PWM)- analog digital converter (ADC) linkage running
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航天飞行对小鼠眼睛的影响及分子反应:航天飞机STS-133任务后的初步观察
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作者 武艳萍 《载人航天信息》 2014年第3期33-44,共12页
航天飞行探测中会出现多种环境应激,包括微重力引起的体液头向转移和辐射暴露。导致航天员视觉损伤的眼睛变化与职业健康有关,但人们对这种复杂环境如何影响眼睛形态与功能则了解甚少。将10~12周龄的BALB/cJ雌性小鼠分为航天飞机STS... 航天飞行探测中会出现多种环境应激,包括微重力引起的体液头向转移和辐射暴露。导致航天员视觉损伤的眼睛变化与职业健康有关,但人们对这种复杂环境如何影响眼睛形态与功能则了解甚少。将10~12周龄的BALB/cJ雌性小鼠分为航天飞机STS.133任务飞行(FLT)组,动物封闭箱(Animal Enclosure Module,AEM)地面对照组,以及透明玻璃箱饲养(Vivarium—housed,VIV)地面对照组。在着陆后第1、5和7天收集眼睛样本,然后对样本进行固定,用于组织学切片。对侧的眼睛用于实时荧光定量(RT-qPCPO,进行基因表达扩增。切片经苏木精染色后,分别再用8-羟基-2-脱鸟苷酸(8.OHdG)、半胱氨酸蛋白酶、胶质细胞原纤维酸性蛋白(GFAP)和β-淀粉样蛋白复染。与地面对照组相比,FLT组小鼠飞行返回后第1天(R+1)的视网膜样本对8-OHdG和半胱氨酸蛋白酶的免疫反应性增加,返回后第7天(R+7)下降。飞行组第R+7天的样本,在视神经后层流区的神经纤维上可见β-淀粉样蛋白。着陆当日,FLT样本视网膜上的氧化及细胞应激反应基因表达上调,到着陆后第7天时水平下降。这些结果提示,暴露在航天飞行中的小鼠,视网膜发生了可逆性分子损伤,为了应对这些变化,在视网膜和视神经上产生了保护性细胞路径。 展开更多
关键词 航天飞行 雌性小鼠 航天飞机 眼睛 分子反应 半胱氨酸蛋白酶 β-淀粉样蛋白 module
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When Finitely Generated δ-Supplemented Modules Are Supplemented
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作者 Rachid Tribak 《Algebra Colloquium》 SCIE CSCD 2015年第1期119-130,共12页
We investigate the structure of rings over which every finitely generated g- supplemented module is supplemented. Some characterizations of this type of rings are given. We establishe some properties of ⊙-δ-suppleme... We investigate the structure of rings over which every finitely generated g- supplemented module is supplemented. Some characterizations of this type of rings are given. We establishe some properties of ⊙-δ-supplemented modules. It is showed that for a ring R, finitely generated δ-supplemented R-modules are supplemented if and only if finitely generated ⊙-δ-supplemented R-modules are ⊙-supplemented. 展开更多
关键词 right -ring (δ-)small submodule (δ-)supplemented module -(δ-)supple-mented module (δ-)local module
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一种CLF芯片与SIM卡芯片连接的方法 被引量:3
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作者 王琪 王东辉 李云岗 《微计算机应用》 2010年第4期73-76,共4页
在NFC技术中,CLF芯片与SIM卡的连接是一个重要问题,本文提出了一种具有自主知识产权的CLF与SIM卡的通信方法,采用新的调制解调方式,使得S2信号在S1信号高低电平时都能传输,实现单线连接NFC与SIM卡,以及它们之间的全双工通信。通过对该... 在NFC技术中,CLF芯片与SIM卡的连接是一个重要问题,本文提出了一种具有自主知识产权的CLF与SIM卡的通信方法,采用新的调制解调方式,使得S2信号在S1信号高低电平时都能传输,实现单线连接NFC与SIM卡,以及它们之间的全双工通信。通过对该方法进行电路级的设计和仿真,验证了该方法的正确性和稳定性。 展开更多
关键词 NFC ( Near Field Communication ) SIM ( subscriber IDENTITY module) SWP( single wire protocol) CLF ( Contact-Less FRONT - end)
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2014年胶粘剂及胶粘带行业国家标准新进展
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《粘接》 CAS 2014年第9期20-20,共1页
一、2014年正式实施的2项国家标准 1.GB/T 29848-2013光伏组件封装用乙烯-醋酸乙烯酯共聚物(EVA)胶膜,2014年4月15日实施。英文名称:Ethylene-vinyl acetate copolymer(EVA)film for encapsulant solar module。
关键词 国家标准 乙烯-醋酸乙烯酯共聚物 胶粘带 胶粘剂 行业 modulE 组件封装 英文名称
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Numbers 1—10的教案设计
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作者 曹馨馨 《山东师范大学外国语学院学报(基础英语教育)》 2005年第2期92-93,共2页
关键词 教案设计 “Numbers1-10” 小学 三年级起点 第一册 module4 英语教学
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Silicon-plus photonics 被引量:2
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作者 Daoxin DAI Yanlong YIN +4 位作者 Longhai YU Hao WU Di LIANG Zhechao WANG Liu LIU 《Frontiers of Optoelectronics》 EI CSCD 2016年第3期436-449,共14页
Silicon photonics has become very popular because of their compatibility with mature CMOS technologies. However, pure silicon is still very difficult to be utilized to obtain various photonic functional devices for la... Silicon photonics has become very popular because of their compatibility with mature CMOS technologies. However, pure silicon is still very difficult to be utilized to obtain various photonic functional devices for large-scale photonic integration due to intrinsic properties. Silicon-plus photonics, which pluses other materials to break the limitation of silicon, is playing a very important role currently and in the future. In this paper, we give a review and discussion on the progresses of siliconplus photonics, including the structures, devices and applications. 展开更多
关键词 silicon-plus hybrid plsamonic PHOTODETECTOR modulATOR graphene -
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24-bit Low-Power Low-Cost Digital Audio Sigma-Delta DAC 被引量:2
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作者 刘渝瑜 高峻 杨晓东 《Tsinghua Science and Technology》 SCIE EI CAS 2011年第1期74-82,共9页
This paper describes a low-power low-cost 24-bit ∑-△ digital-to-analog converter (DAC) for portable digital-audio applications. The interpolation filter uses a no-multiplier scheme to implement the arithmetic unit... This paper describes a low-power low-cost 24-bit ∑-△ digital-to-analog converter (DAC) for portable digital-audio applications. The interpolation filter uses a no-multiplier scheme to implement the arithmetic units and reading-writing common storage scheme for the delay-line to significantly reduce the die area. A 15-level quantizer, third-order, single-stage ∑-△ modulator is employed to reduce the passband quantization noise, relax the out-of-band filtering requirements, and enhance immunity to clock jitter. A data weighted averaging algorithm is used to mitigate the nonlinearity caused by capacitor mismatch. A direct charge transfer switched-capacitor low-pass filter (DCT-SC LPF) is used to reconstruct the analog signal to reduce the kTIC noise and capacitor mismatch effect with a small increase of the power dissipation. The chip was fabricated in the SMIC 0.13 μm 1P5M CMOS process. The cell area of the digital part is 0.056 mm^2 and the total area of the analog part is 0.34 mm^2. The supply voltage is 1.2 V for the digital circuit and 3.3 V for the analog circuit. The power consumption of the analog part is 3.5 mW. The audio DAC achieves a 100 dB dynamic range and an 84 dB peak signal-to-noise-plus-distortion ratio over a 20 kHz passband. The results show that these performances are good enough for high quality portable audio applications. 展开更多
关键词 - digital-to-analog converter - modulator halfband interpolation filter LOW-COST LOW-POWER
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A 4 GHz quadrature output fractional-N frequency synthesizer for an IR-UWB transceiver
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作者 郭诗塔 黄鲁 +2 位作者 袁海泉 冯立松 刘志明 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2010年第3期74-79,共6页
This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver. Designed in a 0.18μm mixed-signal & RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44... This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver. Designed in a 0.18μm mixed-signal & RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44 GHz. By using an 18-bit third-order ∑-△ modulator, the synthesizer achieves a frequency resolution of 15 Hz when the reference frequency is 20 MHz. The measured amplitude mismatch and phase error between I and Q signals are less than 0.1 dB and 0.8° respectively. The measured phase noise is -116 dBc/Hz at 3 MHz offset for a 4 GHz output. Measured spurious tones are lower than -60 dBc. The settling time is within 80°s. The core circuit conupSigmaes only 38.2 mW from a 1.8 V power supply. 展开更多
关键词 frequency synthesizer dual-modulus prescaler - modulator QVCO
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An 18-bit high performance audio ∑-△D/A converter
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作者 张昊 黄小伟 +4 位作者 韩雁 张泽松 韩晓霞 王昊 梁国 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2010年第7期79-84,共6页
A multi-bit quantized high performance sigma-delta(Σ-Δ) audio DAC is presented.Compared to its singlebit counterpart,the multi-bit quantization offers many advantages,such as simplerΣ-Δmodulator circuit,lower cl... A multi-bit quantized high performance sigma-delta(Σ-Δ) audio DAC is presented.Compared to its singlebit counterpart,the multi-bit quantization offers many advantages,such as simplerΣ-Δmodulator circuit,lower clock frequency and smaller spurious tones.With the data weighted average(DWA) mismatch shaping algorithm,element mismatch errors induced by multi-bit quantization can be pushed out of the signal band,hence the noise floor inside the signal band is greatly lowered.To cope with the crosstalk between digital and analog circuits,every analog component is surrounded by a guard ring,which is an innovative attempt.The 18-bit DAC with the above techniques,which is implemented in a 0.18μm mixed-signal CMOS process,occupies a core area of 1.86 mm^2.The measured dynamic range(DR) and peak SNDR are 96 dB and 88 dB,respectively. 展开更多
关键词 digital-to-analog converter Σ-Δmodulator multi-bit quantization SWITCHED-CAPACITOR
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