There is growing interest in developing high-voltage MOSFET devices that can be integrated with low-voltage CMOS digital and analog circuits. In this paper,high-voltage nand p-type MOSFETs are fabricated in a commerci...There is growing interest in developing high-voltage MOSFET devices that can be integrated with low-voltage CMOS digital and analog circuits. In this paper,high-voltage nand p-type MOSFETs are fabricated in a commercial 3.3/ 5V 0.5μm n-well CMOS process without adding any process steps using n-well and p-channel stops. High current and highvoltage transistors with breakdown voltages between 23 and 35V for the nMOS transistors with different laydut parameters and 19V for the pMOS transistors are achieved. This paper also presents the insulation technology and characterization results for these high-voltage devices.展开更多
In this paper, a new voltage-mode (VM), all-pass filter utilizing two second-generation current conveyors and tow differential difference current conveyors (DDCCs) is proposed. This filter uses a number of passive ele...In this paper, a new voltage-mode (VM), all-pass filter utilizing two second-generation current conveyors and tow differential difference current conveyors (DDCCs) is proposed. This filter uses a number of passive elements grounded capacitor. This structure of filter is used to realize a quadrature oscillator. The proposed circuits employ tow optimized differential difference translinear second generation current conveyers (DDCCII). These structures are simulated using the spice simulation in the ADS software and CMOS 0.18 μm process of TSMC technology to confirm the theory. The pole frequency can be tuned in the range of [11.6 - 39.6 MHz] by a simple variation of a DC current.展开更多
文摘Submicron CMOS IC technology, including triple layer resist lithography technology, RIE, LDD, Titanium Salicide, shallow junction, thin gate oxide, no bird's beak isolation and channel's multiple implantation doping technology have been developed. 0.50μm. CMOS integrated circuits have been fabricated using this submicron CMOS process.
文摘设计了一款应用于相控阵雷达系统,工作频段8 GHz^12 GHz,中心频率为10 GHz的5位数字移相器,该移相器采用UMC 0.18μm标准CMOS工艺设计实现.五位移相单元分别为11.25°、22.5°、45°、90°和180°,其中180°移相单元采用高-低通滤波器型结构,其余移相单元采用低通π型滤波器结构.通过合理选择参数模型和拓扑结构,优化版图布局设计,实现了电路性能并给出仿真结果.在工作频率范围内,32种移相状态的相位均方根误差<1.08°,幅度均方根误差<1.14 d B,插入损耗值保持在14 d B^20 d B范围内,版图尺寸为2.85×1.15 mm2.
文摘There is growing interest in developing high-voltage MOSFET devices that can be integrated with low-voltage CMOS digital and analog circuits. In this paper,high-voltage nand p-type MOSFETs are fabricated in a commercial 3.3/ 5V 0.5μm n-well CMOS process without adding any process steps using n-well and p-channel stops. High current and highvoltage transistors with breakdown voltages between 23 and 35V for the nMOS transistors with different laydut parameters and 19V for the pMOS transistors are achieved. This paper also presents the insulation technology and characterization results for these high-voltage devices.
文摘In this paper, a new voltage-mode (VM), all-pass filter utilizing two second-generation current conveyors and tow differential difference current conveyors (DDCCs) is proposed. This filter uses a number of passive elements grounded capacitor. This structure of filter is used to realize a quadrature oscillator. The proposed circuits employ tow optimized differential difference translinear second generation current conveyers (DDCCII). These structures are simulated using the spice simulation in the ADS software and CMOS 0.18 μm process of TSMC technology to confirm the theory. The pole frequency can be tuned in the range of [11.6 - 39.6 MHz] by a simple variation of a DC current.
