We report a low noise continuous-wave （CW） single-frequency 1.5-μm laser source obtained by a singly resonant optical parametric oscillator （SRO） based on periodically poled lithium niobate （PPLN）. The SRO was ...We report a low noise continuous-wave （CW） single-frequency 1.5-μm laser source obtained by a singly resonant optical parametric oscillator （SRO） based on periodically poled lithium niobate （PPLN）. The SRO was pumped by a CW single-frequency Nd：YVO4 laser at 1.06μm. The 1.02 W of CW single-frequency signal laser at 1.5 μm was obtained at pump power of 6 W. At the output power of around 0.75 W, the power stability was better than ±l.5% and no mode-hopping was observed in 30 min and frequency stability was better than 8.5 MHz in 1 min. The signal wavelength could be tuned from 1.57 to 1.59 μm by varying the PPLN temperature. The 1.5-μm laser exhibits low noise characteristics, the intensity noise of the laser reaches the shot noise limit （SNL） at an analysis frequency of 4 MHz and the phase noise is less than 1 dB above the SNL at analysis frequencies above 10 MHz.展开更多
In this paper, we demonstrate the residual phase noise of a few microwave frequency dividers which usually limit the performance of frequency synthesizers. In order to compare these dividers under different operation ...In this paper, we demonstrate the residual phase noise of a few microwave frequency dividers which usually limit the performance of frequency synthesizers. In order to compare these dividers under different operation frequencies, we calculate additional time jitters of these dividers by using the measured phase noise. The time jitters are various from -0.1 fs to 43 fs in a bandwidth from 1 Hz to 100 Hz in dependent of models and operation frequencies. The HMC series frequency dividers exhibit outstanding performance for high operation frequencies, and the time jitters can be sub-fs. The time jitters of SP8401, MC10EP139, and MC100LVEL34 are comparable or even below that of HMC series for low operation frequencies.展开更多
This paper proposes CMOS LC-tank divide-by-3 injection locked frequency dividers(ILFDs)fabricated in 0.18μn and 90nm CMOS process and describes the circuit design,operation principle and measurement results of the IL...This paper proposes CMOS LC-tank divide-by-3 injection locked frequency dividers(ILFDs)fabricated in 0.18μn and 90nm CMOS process and describes the circuit design,operation principle and measurement results of the ILFDs.The ILFDs use two injection series-MOSFETs across the LC resonator and a differential injection signal is applied to the gates of injection MOSFETs.The direct-injection divide-by-3 ILFDs are potential for radio-frequency application and can have wide locking range.展开更多
A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 presc...A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 prescaler and by 128-255 multi-modulus frequency divider. In the circuit design, power and speed trade-offs are analyzed for the prescaler, and power optimization techniques are used according to the input frequency of each divider cell for the 128-255 multimodulus frequency divider. The chip is designed with ESD protected I/O PAD. The dividers chain can work as high as 2.4GHz with a single ended input signal and beyond 2.6GHz with differential input signals. The dual-modulus prescaler consumes 11mA of current while the 128-255 multi-modulus frequency divider consumes 17mA of current with a 3.3V power supply. The core area of the die without PAD is 0.65mm × 0.3mm. This programmable multi-modulus frequency divider can be used for 2.4GHz ISM band PLL-based frequency synthesizers. To our knowledge, this is the first reported multi-modulus frequency divider with this structure in China.展开更多
An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler （DMP） and programmable ＆ pulse swallow divider,different methods ...An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler （DMP） and programmable ＆ pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively. Using a DMP high speed, lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps. The flexibility and reusability of the progrs, mmable divider is high;its use could be extended to many complicated frequency synthesizers. By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.展开更多
A scheme of a frequency-hopping frequency-synthesizer applied to a Bluetooth ratio frequency （RF） front-end is presented,and design of a voltage controlled oscillator （VCO） and dual-modulus prescaler are focused o...A scheme of a frequency-hopping frequency-synthesizer applied to a Bluetooth ratio frequency （RF） front-end is presented,and design of a voltage controlled oscillator （VCO） and dual-modulus prescaler are focused on.It is fabricated in a 0.18 μm mixed-signal CMOS （complementary metal-oxide-semiconductor transistor） process.The power dissipation of VCO is low and a stable performance is gained.The measured phase noise of VCO at 2.4 GHz is less than -114.32 dBc/Hz.The structure of the DMP is optimized and a novel D-latch integrated with ＂OR＂ logic gate is used.The measured results show that the chip can work well under a 1.8 V power supply.The power dissipation of the core part in a dual modulus prescaler is only 5.76 mW.An RMS jitter of 2 ps is measured on the output signal at 118.3 MHz.It is less than 0.02% of the clock period.展开更多
This paper describes a wideband low phase noise frequency synthesizer.It operates in the multi-band including digital radio mondiale DRM digital audio broadcasting DAB amplitude modulation AM and frequency modulation ...This paper describes a wideband low phase noise frequency synthesizer.It operates in the multi-band including digital radio mondiale DRM digital audio broadcasting DAB amplitude modulation AM and frequency modulation FM .In order to cover the signals of the overall frequencies a novel frequency planning and a new structure are proposed. A wide-band low-phase-noise low-power voltage-control oscillator VCO and a high speed wide band high frequency division ratio pulse swallow frequency divider with a low power consumption are presented.The monolithic DRM/DAB/AM/FM frequency synthesizer chip is also fabricated in a SMIC＇s 0.18-μm CMOS process.The die area is 1 425 μm ×795 μm including the test buffer and pads. The measured results show that the VCO operating frequency range is from 2.22 to 3.57 GHz the measured phase noise of the VCO is 120.22 dBc/Hz at 1 MHz offset the pulse swallow frequency divider operation frequency is from 0.9 to 3.4 GHz.The phase noise in the phase-locked loop PLL is-59.52 dBc/Hz at 10 kHz offset and fits for the demand of the DRM/DAB/AM/FM RF front-end. The proposed frequency synthesizer consumes 47 mW including test buffer under a 1.8 V supply.展开更多
The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communi...The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communication systems, is presented. By cooperating with a dual-modulus prescaler, this divider can realize an integer frequency division from 926 to 1 387. Besides the traditional standard cell design flow, such as logic synthesis, placement and routing, the interactions between front-end and back-end are also considered to optimize the design flow under deep submicron technology. By back-annotating the back-end information to front-end design, a custom wire-load model is created which is more practical compared with the default model. This divider has been fabricated in TSMC 0. 18μm CMOS technology using Artisan standard cell library. The chip area is 675 μm × 475 μm and the power consumption is about 2 mW under a 1.8 V power supply. Measurement results show that it works correctly and can realize a frequency division with high precision.展开更多
An 1∶8 frequency divider is designed and realized in a 0 35μm standard CMOS technology.The chip consists of three stages of 1∶2 divider cells,which are constructed with source couple logic (SCL) flip flops.By rev...An 1∶8 frequency divider is designed and realized in a 0 35μm standard CMOS technology.The chip consists of three stages of 1∶2 divider cells,which are constructed with source couple logic (SCL) flip flops.By revising the traditional topology of SCL flip flop,a divider with better performances is got.The results of measurement show that the whole chip achieves the frequency division at more than 8 5GHz.Each 1∶2 divider consumes about 11mW from a 3 3V supply.The divider can be used in RF and optic fiber transceivers and other high speed systems.展开更多
A novel edge-triggered D-flip-flop based on a resonant tunneling diode （RTD） is proposed and used to construct a binary frequency divider. The design is discussed in detail and the performance of the circuit is veri...A novel edge-triggered D-flip-flop based on a resonant tunneling diode （RTD） is proposed and used to construct a binary frequency divider. The design is discussed in detail and the performance of the circuit is verified using SPICE. Relying on the nonlinear characteristics of RTD,we reduced the number of components used in our DFF circuit to only half of that required using conventional CMOS SCFL technology.展开更多
A layout and connection optimization for static frequency divider is presented. The layout optimization provides a new circle topology transistors placement and reasonable connection structure, which reduces the paras...A layout and connection optimization for static frequency divider is presented. The layout optimization provides a new circle topology transistors placement and reasonable connection structure, which reduces the parasitic effectively and enables self-oscillation frequency enhancement. Besides, bandwidth enhancement techniques based on a center-tap capacitor in input balun design and inductive peaking in latch design are adopted to improve further high frequency performance with low power consumption. As a proof of concept, design of a divide-by-2 static frequency divider in 0.13 μm SiGe BiCMOS technology is reported. With single-ended input clock signal, the divider is measured to be operated from 40 to 90 GHz. Phase noise measurements of a 90 GHz input clock signal indicate ideal behavior with no measurable noise contribution from the divider. The divider followed by a buffer that can deliver more than-10 dBm output power, which is sufficient to drive succeeding stage. To the author's knowledge, the divider exhibits a competitive power dissipation and the highest FOM among silicon based frequency dividers that operating higher than 70 GHz.展开更多
The design of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for transmitter and receiver in IEEE 802. 11 a standard, is investigated. The main ...The design of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for transmitter and receiver in IEEE 802. 11 a standard, is investigated. The main steps in very large-scale integration （VLSI） design flow such as logic synthesis, floorplan and placement ＆ routing （P ＆ R） are introduced. By back-annotating the back-end information to the front-end design, the custom wire-load model is created and used for optimizing the design flow under deep submicron technology. The programmable frequency divider is implemented based on Artisan TSMC （Taiwan Semicoductor Manufacturing Co. Ltd. ）0. 18μm CMOS （complementary metal-oxide-semiconductor） standard cells and fabricated. The Chip area is 1 360. 5μm^2 and can work in the range of 100 to 200 MHz. The measurement results indicate that the design conforms to the frequency division precision.展开更多
A fractional frequency divider based on phase switching and negative feedback delta-sigma modulator(NF-DSM) is presented. The phase switching circuit, realized by switching 8 signals generated by a divider-by-4 circui...A fractional frequency divider based on phase switching and negative feedback delta-sigma modulator(NF-DSM) is presented. The phase switching circuit, realized by switching 8 signals generated by a divider-by-4 circuit, is adopted to reduce the frequency division step. The NF-DSM, which can obtain smooth output spectra, is proposed to generate the fractional part of the division ratio, moreover, the integer part of the division ratio is realized by a divider-by-2/3 circuit chain. Fabricated in TSMC 0.18 μm RF CMOS technology, the fractional frequency divider achieves a measured operation frequency from 0.5 GHz to 8 GHz. With a 1.8 V supply voltage, the maximum current consumption of the whole divider is 17.5 mA, and the chip area is 0.58 mm^2, including the pads.展开更多
In this paper, a 30 GHz wide locking-range (26.2 GHz-35.7 GHz) direct injection-locked frequency divider (ILFD), which operating in the millimeter-wave (MMW) band, is presented. The locking range of the ILFD is extend...In this paper, a 30 GHz wide locking-range (26.2 GHz-35.7 GHz) direct injection-locked frequency divider (ILFD), which operating in the millimeter-wave (MMW) band, is presented. The locking range of the ILFD is extended by using differential injection topology. Besides, varactors are used in RLC resonant tank for extending the frequency tuning range. The post simulation results show that a wide locking-range of 9.5 GHz (30.7%) is achieved. When the VCO output frequency varies from 26.85 GHz to 34.42 GHz, the proposed ILFD can achieve divide-by-two correctly. Designed in 0.13 μm CMOS technology, the ILFD occupies a core area of 0.76 mm2 while drawing 7 mA of current from 2.5 V power supply.展开更多
基金supported by the National Natural Science Foundation of China(Grant No.60878003)the Science Fund for Excellent Research Team of the National Natural Science Foundation of China(Grant No.60821004)the National Basic Research Program of China(Grant No.2010CB923101)
文摘We report a low noise continuous-wave （CW） single-frequency 1.5-μm laser source obtained by a singly resonant optical parametric oscillator （SRO） based on periodically poled lithium niobate （PPLN）. The SRO was pumped by a CW single-frequency Nd：YVO4 laser at 1.06μm. The 1.02 W of CW single-frequency signal laser at 1.5 μm was obtained at pump power of 6 W. At the output power of around 0.75 W, the power stability was better than ±l.5% and no mode-hopping was observed in 30 min and frequency stability was better than 8.5 MHz in 1 min. The signal wavelength could be tuned from 1.57 to 1.59 μm by varying the PPLN temperature. The 1.5-μm laser exhibits low noise characteristics, the intensity noise of the laser reaches the shot noise limit （SNL） at an analysis frequency of 4 MHz and the phase noise is less than 1 dB above the SNL at analysis frequencies above 10 MHz.
基金supported by the National Natural Science Foundation of China under Grant No.91336101 and No.61127901the West Light Foundation of the Chinese Academy of Sciences under Grant No.2013ZD02
文摘In this paper, we demonstrate the residual phase noise of a few microwave frequency dividers which usually limit the performance of frequency synthesizers. In order to compare these dividers under different operation frequencies, we calculate additional time jitters of these dividers by using the measured phase noise. The time jitters are various from -0.1 fs to 43 fs in a bandwidth from 1 Hz to 100 Hz in dependent of models and operation frequencies. The HMC series frequency dividers exhibit outstanding performance for high operation frequencies, and the time jitters can be sub-fs. The time jitters of SP8401, MC10EP139, and MC100LVEL34 are comparable or even below that of HMC series for low operation frequencies.
文摘This paper proposes CMOS LC-tank divide-by-3 injection locked frequency dividers(ILFDs)fabricated in 0.18μn and 90nm CMOS process and describes the circuit design,operation principle and measurement results of the ILFDs.The ILFDs use two injection series-MOSFETs across the LC resonator and a differential injection signal is applied to the gates of injection MOSFETs.The direct-injection divide-by-3 ILFDs are potential for radio-frequency application and can have wide locking range.
文摘A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 prescaler and by 128-255 multi-modulus frequency divider. In the circuit design, power and speed trade-offs are analyzed for the prescaler, and power optimization techniques are used according to the input frequency of each divider cell for the 128-255 multimodulus frequency divider. The chip is designed with ESD protected I/O PAD. The dividers chain can work as high as 2.4GHz with a single ended input signal and beyond 2.6GHz with differential input signals. The dual-modulus prescaler consumes 11mA of current while the 128-255 multi-modulus frequency divider consumes 17mA of current with a 3.3V power supply. The core area of the die without PAD is 0.65mm × 0.3mm. This programmable multi-modulus frequency divider can be used for 2.4GHz ISM band PLL-based frequency synthesizers. To our knowledge, this is the first reported multi-modulus frequency divider with this structure in China.
文摘An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler （DMP） and programmable ＆ pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively. Using a DMP high speed, lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps. The flexibility and reusability of the progrs, mmable divider is high;its use could be extended to many complicated frequency synthesizers. By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.
文摘A scheme of a frequency-hopping frequency-synthesizer applied to a Bluetooth ratio frequency （RF） front-end is presented,and design of a voltage controlled oscillator （VCO） and dual-modulus prescaler are focused on.It is fabricated in a 0.18 μm mixed-signal CMOS （complementary metal-oxide-semiconductor transistor） process.The power dissipation of VCO is low and a stable performance is gained.The measured phase noise of VCO at 2.4 GHz is less than -114.32 dBc/Hz.The structure of the DMP is optimized and a novel D-latch integrated with ＂OR＂ logic gate is used.The measured results show that the chip can work well under a 1.8 V power supply.The power dissipation of the core part in a dual modulus prescaler is only 5.76 mW.An RMS jitter of 2 ps is measured on the output signal at 118.3 MHz.It is less than 0.02% of the clock period.
基金The Research Project of Science and Technology at the University of Inner Mongolia Autonomous Region(No.NJZY11016)the Innovation Fund of the Ministry of Science and Technology for Small and Medium Sized Enterprises of China(No.11C26213211234)
文摘This paper describes a wideband low phase noise frequency synthesizer.It operates in the multi-band including digital radio mondiale DRM digital audio broadcasting DAB amplitude modulation AM and frequency modulation FM .In order to cover the signals of the overall frequencies a novel frequency planning and a new structure are proposed. A wide-band low-phase-noise low-power voltage-control oscillator VCO and a high speed wide band high frequency division ratio pulse swallow frequency divider with a low power consumption are presented.The monolithic DRM/DAB/AM/FM frequency synthesizer chip is also fabricated in a SMIC＇s 0.18-μm CMOS process.The die area is 1 425 μm ×795 μm including the test buffer and pads. The measured results show that the VCO operating frequency range is from 2.22 to 3.57 GHz the measured phase noise of the VCO is 120.22 dBc/Hz at 1 MHz offset the pulse swallow frequency divider operation frequency is from 0.9 to 3.4 GHz.The phase noise in the phase-locked loop PLL is-59.52 dBc/Hz at 10 kHz offset and fits for the demand of the DRM/DAB/AM/FM RF front-end. The proposed frequency synthesizer consumes 47 mW including test buffer under a 1.8 V supply.
基金The National Natural Science Foundation of China(No.60472057)
文摘The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communication systems, is presented. By cooperating with a dual-modulus prescaler, this divider can realize an integer frequency division from 926 to 1 387. Besides the traditional standard cell design flow, such as logic synthesis, placement and routing, the interactions between front-end and back-end are also considered to optimize the design flow under deep submicron technology. By back-annotating the back-end information to front-end design, a custom wire-load model is created which is more practical compared with the default model. This divider has been fabricated in TSMC 0. 18μm CMOS technology using Artisan standard cell library. The chip area is 675 μm × 475 μm and the power consumption is about 2 mW under a 1.8 V power supply. Measurement results show that it works correctly and can realize a frequency division with high precision.
文摘An 1∶8 frequency divider is designed and realized in a 0 35μm standard CMOS technology.The chip consists of three stages of 1∶2 divider cells,which are constructed with source couple logic (SCL) flip flops.By revising the traditional topology of SCL flip flop,a divider with better performances is got.The results of measurement show that the whole chip achieves the frequency division at more than 8 5GHz.Each 1∶2 divider consumes about 11mW from a 3 3V supply.The divider can be used in RF and optic fiber transceivers and other high speed systems.
文摘A novel edge-triggered D-flip-flop based on a resonant tunneling diode （RTD） is proposed and used to construct a binary frequency divider. The design is discussed in detail and the performance of the circuit is verified using SPICE. Relying on the nonlinear characteristics of RTD,we reduced the number of components used in our DFF circuit to only half of that required using conventional CMOS SCFL technology.
基金supported by National Natural Science Foundation of China under Grant 61701114the National Science and Technology Major Project under Grant 2017ZX03001020the Scientific Research Foundation of Graduate School of Southeast University (Grant No. YBJJ1811)
文摘A layout and connection optimization for static frequency divider is presented. The layout optimization provides a new circle topology transistors placement and reasonable connection structure, which reduces the parasitic effectively and enables self-oscillation frequency enhancement. Besides, bandwidth enhancement techniques based on a center-tap capacitor in input balun design and inductive peaking in latch design are adopted to improve further high frequency performance with low power consumption. As a proof of concept, design of a divide-by-2 static frequency divider in 0.13 μm SiGe BiCMOS technology is reported. With single-ended input clock signal, the divider is measured to be operated from 40 to 90 GHz. Phase noise measurements of a 90 GHz input clock signal indicate ideal behavior with no measurable noise contribution from the divider. The divider followed by a buffer that can deliver more than-10 dBm output power, which is sufficient to drive succeeding stage. To the author's knowledge, the divider exhibits a competitive power dissipation and the highest FOM among silicon based frequency dividers that operating higher than 70 GHz.
基金The National Natural Science Foundation of China(No60472057)
文摘The design of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for transmitter and receiver in IEEE 802. 11 a standard, is investigated. The main steps in very large-scale integration （VLSI） design flow such as logic synthesis, floorplan and placement ＆ routing （P ＆ R） are introduced. By back-annotating the back-end information to the front-end design, the custom wire-load model is created and used for optimizing the design flow under deep submicron technology. The programmable frequency divider is implemented based on Artisan TSMC （Taiwan Semicoductor Manufacturing Co. Ltd. ）0. 18μm CMOS （complementary metal-oxide-semiconductor） standard cells and fabricated. The Chip area is 1 360. 5μm^2 and can work in the range of 100 to 200 MHz. The measurement results indicate that the design conforms to the frequency division precision.
基金Supported by the National Natural Science Foundation of China(No.61674037)National Key Research and Development Program of China(No.2016YFC0800400)the Priority Academic Program Development of Jiangsu Higher Education Institutions
文摘A fractional frequency divider based on phase switching and negative feedback delta-sigma modulator(NF-DSM) is presented. The phase switching circuit, realized by switching 8 signals generated by a divider-by-4 circuit, is adopted to reduce the frequency division step. The NF-DSM, which can obtain smooth output spectra, is proposed to generate the fractional part of the division ratio, moreover, the integer part of the division ratio is realized by a divider-by-2/3 circuit chain. Fabricated in TSMC 0.18 μm RF CMOS technology, the fractional frequency divider achieves a measured operation frequency from 0.5 GHz to 8 GHz. With a 1.8 V supply voltage, the maximum current consumption of the whole divider is 17.5 mA, and the chip area is 0.58 mm^2, including the pads.
文摘In this paper, a 30 GHz wide locking-range (26.2 GHz-35.7 GHz) direct injection-locked frequency divider (ILFD), which operating in the millimeter-wave (MMW) band, is presented. The locking range of the ILFD is extended by using differential injection topology. Besides, varactors are used in RLC resonant tank for extending the frequency tuning range. The post simulation results show that a wide locking-range of 9.5 GHz (30.7%) is achieved. When the VCO output frequency varies from 26.85 GHz to 34.42 GHz, the proposed ILFD can achieve divide-by-two correctly. Designed in 0.13 μm CMOS technology, the ILFD occupies a core area of 0.76 mm2 while drawing 7 mA of current from 2.5 V power supply.
