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Structure design and film process optimization for metal-gate stress in 20 nm nMOS devices
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作者 付作振 殷华湘 +3 位作者 马小龙 柴淑敏 高建峰 陈大鹏 《Journal of Semiconductors》 EI CAS CSCD 2013年第6期165-169,共5页
The optimizations to metal gate structure and film process were extensively investigated for great metalgate stress(MGS) in 20 nm high-k/metal-gate-last(HKVMG-last) nMOS devices.The characteristics of advanced MGS... The optimizations to metal gate structure and film process were extensively investigated for great metalgate stress(MGS) in 20 nm high-k/metal-gate-last(HKVMG-last) nMOS devices.The characteristics of advanced MGS technologies on device performances were studied through a process and device simulation by TCAD tools. The metal gate electrode with different stress values(0 to—6 GPa) was implemented in the device simulation along with other traditional process-induced-strain(PIS) technologies like e-SiC and nitride capping layer.The MGS demonstrated a great enhancing effect on channel carriers transporting in the device as device pitch scaling down.In addition,the novel structure for a tilted gate electrode was proposed and relationships between the tilt angle and channel stress were investigated.Also with a new method of fully stressed replacement metal gate(FSRMG) and using plane-shape-HfO to substitute U-shape-HfO,the effect of MGS was improved.For greater film stress in the metal gate,the process conditions for physical vapor deposition(PVD) TiN-x- were optimized.The maximum compressive stress of—6.5 GPa TiN_x was achieved with thinner film and greater RF power as well as about 6 sccm N ratio. 展开更多
关键词 metal gate stress 20 nm cmos devices high-k/metal gate PVD TiN_x
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