This paper deals with a binocular 3-D computer vision system based on the hierarchicalmatching of edge features, Frei and Chen operator is used to extract the edge. The averagegradients of an image obtained by two iso...This paper deals with a binocular 3-D computer vision system based on the hierarchicalmatching of edge features, Frei and Chen operator is used to extract the edge. The averagegradients of an image obtained by two isotropic operators are non-equal quantized andthresholded in an angle, Edge features are extracted after passing a preemphasis transferfunction which can equalize, the noise affection. Binary edge images are decomposed into apyramid structure which is stored and searched using llliffe’s location method. Corre-sponding points are used to determine the range data using triangulation based on an improvedTrivedi’s formula. In calibration the authors set the optical axes of the two cameras parallelto simplify the calculation, A 3 rd order Householder transform is used to solve the compati-ble coupled equations.展开更多
Hierarchical art was used to solve the mixed mode placement for three dimensional （3-D） integrated circuit design. The 3-D placement flow stream includes hierarchical clustering, hierarchical 3-D floorplanning, vert...Hierarchical art was used to solve the mixed mode placement for three dimensional （3-D） integrated circuit design. The 3-D placement flow stream includes hierarchical clustering, hierarchical 3-D floorplanning, vertical via mapping, and recursive two dimensional （2-D） global/detailed placement phases. With state-of-the-art clustering and de-clustering phases, the design complexity was reduced to enhance the placement algorithm efficiency and capacity. The 3-D floorplanning phase solved the layer assignment problem and controlled the number of vertical vias. The vertical via mapping transformed the 3-D placement problem to a set of 2-D placement sub-problems, which not only simplifies the original 3-D placement problem, but also generates the vertical via assignment solution for the routing phase. The design optimizes both the wire length and the thermal load in the floorplan and placement phases to improve the performance and reliability of 3-D integrate circuits. Experiments on IBM benchmarks show that the total wire length is reduced from 15% to 35% relative to 2-D placement with two to four stacked layers, with the number of vertical vias minimized to satisfy a pre-defined upper bound constraint. The maximum temperature is reduced by 16% with two-stage optimization on four stacked layers.展开更多
文摘This paper deals with a binocular 3-D computer vision system based on the hierarchicalmatching of edge features, Frei and Chen operator is used to extract the edge. The averagegradients of an image obtained by two isotropic operators are non-equal quantized andthresholded in an angle, Edge features are extracted after passing a preemphasis transferfunction which can equalize, the noise affection. Binary edge images are decomposed into apyramid structure which is stored and searched using llliffe’s location method. Corre-sponding points are used to determine the range data using triangulation based on an improvedTrivedi’s formula. In calibration the authors set the optical axes of the two cameras parallelto simplify the calculation, A 3 rd order Householder transform is used to solve the compati-ble coupled equations.
基金Supported by the National Natural Science Foundation of China (Nos.60833004 and 60876026)the 3-D Floorplanning and Placement Project of the Intel Corporation
文摘Hierarchical art was used to solve the mixed mode placement for three dimensional （3-D） integrated circuit design. The 3-D placement flow stream includes hierarchical clustering, hierarchical 3-D floorplanning, vertical via mapping, and recursive two dimensional （2-D） global/detailed placement phases. With state-of-the-art clustering and de-clustering phases, the design complexity was reduced to enhance the placement algorithm efficiency and capacity. The 3-D floorplanning phase solved the layer assignment problem and controlled the number of vertical vias. The vertical via mapping transformed the 3-D placement problem to a set of 2-D placement sub-problems, which not only simplifies the original 3-D placement problem, but also generates the vertical via assignment solution for the routing phase. The design optimizes both the wire length and the thermal load in the floorplan and placement phases to improve the performance and reliability of 3-D integrate circuits. Experiments on IBM benchmarks show that the total wire length is reduced from 15% to 35% relative to 2-D placement with two to four stacked layers, with the number of vertical vias minimized to satisfy a pre-defined upper bound constraint. The maximum temperature is reduced by 16% with two-stage optimization on four stacked layers.
