According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barrier...According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barriers. Overcoming these pitch-scaling induced barriers requires integrating the most advanced process technologies into product manufacturing. This paper reviews and discusses new technology applications that could be potentially integrated into 32nm node in the following areas：extension of immersion lithography,mobility enhancement substrate technology,metal/ high-k （MHK） gate stack, ultra-shallow junction （USJ） and other strain enhancement engineering methods, including stress proximity effect （SPT）, dual stress liner （DSL）, stress memorization technique （SMT）, high aspect ratio process （HARP） for STI and PMD,embedded SiGe （for pFET） and SiC （for nFET） source/drain （S/D） using selective epitaxial growth （SEG） method,metallization for middle of line （MOL） and back-end of line （BEOL） ,and ultra low-k （ULK） integration.展开更多
This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors. The SRAM cell is based on 32nm silicon-on-insulator （SO1） technology node. It consists of two access transistors and two pull-down tran...This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors. The SRAM cell is based on 32nm silicon-on-insulator （SO1） technology node. It consists of two access transistors and two pull-down transistors. The pull-down transistors have larger channel length than the access transistors. Due to the significant short channel effect of small-size MOS transistors, the access transistors have much larger leakage current than the pull-down transistors,enabling the SRAM cell to maintain logic ＂1＂ while in standby. The storage node voltages of the cell are fed back to the back-gates of the access transistors,enabling the stable ＂read＂ operation of the cell. The use of back-gate feedback also helps to im- prove the static noise margin （SNM） of the cell. The proposed SRAM cell has smaller area than conventional bulk 6T SRAM cells and 4T SRAM cells. The speed and power dissipation of the SRAM cell are simulated and discussed. The SRAM cell can operate with a 0. 5V supply voltage.展开更多
With the relentless densification of interconnected circuitry dictated by Moore’ s Law,the CMP manufacture of such delicate wafers requires the significant reduction of polishing pressure of integrated circuits,not o...With the relentless densification of interconnected circuitry dictated by Moore’ s Law,the CMP manufacture of such delicate wafers requires the significant reduction of polishing pressure of integrated circuits,not only globally,but also locally on every tip of the pad asperities.Conventional diamond disks used for dressing the polyurethane pads cannot produce asperities to achieve such uniformity.A new design of diamond disk was fabricated by casting diamond film on a silicon wafer that contains patterned etching pits. This silicon mold was subsequently removed by dissolution in a hydroxide solution.The diamond film followed the profile of the etching pits on silicon to form pyramids of identical in size and shape.The variation of their tip heights was in microns of single digit that was about one order of magnitude smaller than conventional diamond disks for CMP production.Moreover,the diamond film contained no metal that might contaminate the circuits on polished wafer during a CMP operation.The continuous diamond film could resist any corrosive attack by slurry of acid or base.Consequently,in-situ dressing during CMP is possible that may improve wafer uniformity and production throughput.This ideal diamond disk(IDD) is designed for the future manufacture of advanced semiconductor chips with node sizes of 32 nm or smaller.展开更多
文摘According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barriers. Overcoming these pitch-scaling induced barriers requires integrating the most advanced process technologies into product manufacturing. This paper reviews and discusses new technology applications that could be potentially integrated into 32nm node in the following areas：extension of immersion lithography,mobility enhancement substrate technology,metal/ high-k （MHK） gate stack, ultra-shallow junction （USJ） and other strain enhancement engineering methods, including stress proximity effect （SPT）, dual stress liner （DSL）, stress memorization technique （SMT）, high aspect ratio process （HARP） for STI and PMD,embedded SiGe （for pFET） and SiC （for nFET） source/drain （S/D） using selective epitaxial growth （SEG） method,metallization for middle of line （MOL） and back-end of line （BEOL） ,and ultra low-k （ULK） integration.
文摘This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors. The SRAM cell is based on 32nm silicon-on-insulator （SO1） technology node. It consists of two access transistors and two pull-down transistors. The pull-down transistors have larger channel length than the access transistors. Due to the significant short channel effect of small-size MOS transistors, the access transistors have much larger leakage current than the pull-down transistors,enabling the SRAM cell to maintain logic ＂1＂ while in standby. The storage node voltages of the cell are fed back to the back-gates of the access transistors,enabling the stable ＂read＂ operation of the cell. The use of back-gate feedback also helps to im- prove the static noise margin （SNM） of the cell. The proposed SRAM cell has smaller area than conventional bulk 6T SRAM cells and 4T SRAM cells. The speed and power dissipation of the SRAM cell are simulated and discussed. The SRAM cell can operate with a 0. 5V supply voltage.
文摘With the relentless densification of interconnected circuitry dictated by Moore’ s Law,the CMP manufacture of such delicate wafers requires the significant reduction of polishing pressure of integrated circuits,not only globally,but also locally on every tip of the pad asperities.Conventional diamond disks used for dressing the polyurethane pads cannot produce asperities to achieve such uniformity.A new design of diamond disk was fabricated by casting diamond film on a silicon wafer that contains patterned etching pits. This silicon mold was subsequently removed by dissolution in a hydroxide solution.The diamond film followed the profile of the etching pits on silicon to form pyramids of identical in size and shape.The variation of their tip heights was in microns of single digit that was about one order of magnitude smaller than conventional diamond disks for CMP production.Moreover,the diamond film contained no metal that might contaminate the circuits on polished wafer during a CMP operation.The continuous diamond film could resist any corrosive attack by slurry of acid or base.Consequently,in-situ dressing during CMP is possible that may improve wafer uniformity and production throughput.This ideal diamond disk(IDD) is designed for the future manufacture of advanced semiconductor chips with node sizes of 32 nm or smaller.
