随着芯片集成度的提高,三维片上系统(three-dimensional System on Chip,3DSoC)是集成电路发展的必然趋势,其中可测性设计成为研究的重点.为了降低测试代价,提出一种符合工业实际的多频测试架构及适用于该架构的测试算法,并结合功耗对...随着芯片集成度的提高,三维片上系统(three-dimensional System on Chip,3DSoC)是集成电路发展的必然趋势,其中可测性设计成为研究的重点.为了降低测试代价,提出一种符合工业实际的多频测试架构及适用于该架构的测试算法,并结合功耗对测试架构进行了仿真实验.实验结果表明,与传统的SoC相比,在同样TAM测试数据位宽数限制下,多频架构的3DSoC测试时间更短,测试代价更小.展开更多
光刻仿真是SOC(System On Chip)光刻工艺的重要环节,为了实现仿真数据3D可视化,在光刻仿真程序SPLAT(Simulation of Projection Lens Aberrations via TCCs)基础上,提出了自动排序算法对SPLAT输出数据进行重新排列以便三维建模,建立了...光刻仿真是SOC(System On Chip)光刻工艺的重要环节,为了实现仿真数据3D可视化,在光刻仿真程序SPLAT(Simulation of Projection Lens Aberrations via TCCs)基础上,提出了自动排序算法对SPLAT输出数据进行重新排列以便三维建模,建立了光照强度与深度转换模型,将光照强度数值转变为3D可视化的深度数据,论文最后设计了3D实时图形仿真程序并进行了实验。实验证明了自动排序算法以及转换模型的正确性和先进性,为超大规模SOC数据的3D交互式实时显示奠定了基础。展开更多
The ever-increasing complexity of on-chip interconnection poses great challenges for the architecture of conventional system-on-chip(SoC) in semiconductor industry. The rapid development of process technology enables ...The ever-increasing complexity of on-chip interconnection poses great challenges for the architecture of conventional system-on-chip(SoC) in semiconductor industry. The rapid development of process technology enables the creation of stacked 3-dimensional(3 D) SoC by means of through-silicon-via(TSV). Stacked 3 D SoC testing consists of two major issues, test architecture optimization and test scheduling. This paper proposed game theory based optimization of test scheduling and test architecture to achieve win-win result as well as individual rationality for each player in a game. Game theory helps to achieve equilibrium between two correlated sides to find an optimal solution. Experimental results on handcrafted 3 D SoCs built from ITC'2 benchmarks demonstrate that the proposed approach achieves comparable or better test times at negligible computing time.展开更多
本文提出一种三维片上系统(3D So C)的测试策略,针对硅通孔(TSV,Through Silicon Vias)互连技术的3D So C绑定中和绑定后的测试进行优化,由于测试时间和用于测试的TSV数目都会对最终的测试成本产生很大的影响,本文的优化策略在有效降低...本文提出一种三维片上系统(3D So C)的测试策略,针对硅通孔(TSV,Through Silicon Vias)互连技术的3D So C绑定中和绑定后的测试进行优化,由于测试时间和用于测试的TSV数目都会对最终的测试成本产生很大的影响,本文的优化策略在有效降低测试时间的同时,还可以控制测试用的TSV数目,从而降低了测试成本.实验结果表明,本文的测试优化策略与同类仅考虑降低测试时间的策略相比,可以进一步降低约20%的测试成本.展开更多
文摘随着芯片集成度的提高,三维片上系统(three-dimensional System on Chip,3DSoC)是集成电路发展的必然趋势,其中可测性设计成为研究的重点.为了降低测试代价,提出一种符合工业实际的多频测试架构及适用于该架构的测试算法,并结合功耗对测试架构进行了仿真实验.实验结果表明,与传统的SoC相比,在同样TAM测试数据位宽数限制下,多频架构的3DSoC测试时间更短,测试代价更小.
文摘光刻仿真是SOC(System On Chip)光刻工艺的重要环节,为了实现仿真数据3D可视化,在光刻仿真程序SPLAT(Simulation of Projection Lens Aberrations via TCCs)基础上,提出了自动排序算法对SPLAT输出数据进行重新排列以便三维建模,建立了光照强度与深度转换模型,将光照强度数值转变为3D可视化的深度数据,论文最后设计了3D实时图形仿真程序并进行了实验。实验证明了自动排序算法以及转换模型的正确性和先进性,为超大规模SOC数据的3D交互式实时显示奠定了基础。
基金supported by the Support Project of High-Level Teachers in Beijing Municipal Universities in the Period of the13th Five-Year Plan(CIT&TCD 201704069)the Advanced Research Project for Science and Technology Development of Harbin Normal University(901-220601094)the Natural ScienceFoundationofHeilongjiangProvince(JJ2019LH0418)
文摘The ever-increasing complexity of on-chip interconnection poses great challenges for the architecture of conventional system-on-chip(SoC) in semiconductor industry. The rapid development of process technology enables the creation of stacked 3-dimensional(3 D) SoC by means of through-silicon-via(TSV). Stacked 3 D SoC testing consists of two major issues, test architecture optimization and test scheduling. This paper proposed game theory based optimization of test scheduling and test architecture to achieve win-win result as well as individual rationality for each player in a game. Game theory helps to achieve equilibrium between two correlated sides to find an optimal solution. Experimental results on handcrafted 3 D SoCs built from ITC'2 benchmarks demonstrate that the proposed approach achieves comparable or better test times at negligible computing time.
文摘本文提出一种三维片上系统(3D So C)的测试策略,针对硅通孔(TSV,Through Silicon Vias)互连技术的3D So C绑定中和绑定后的测试进行优化,由于测试时间和用于测试的TSV数目都会对最终的测试成本产生很大的影响,本文的优化策略在有效降低测试时间的同时,还可以控制测试用的TSV数目,从而降低了测试成本.实验结果表明,本文的测试优化策略与同类仅考虑降低测试时间的策略相比,可以进一步降低约20%的测试成本.
