Synergistic Coupling of Sulfide Electrolyte and Integrated 3D FeS_(2)Electrode Toward Long-Cycling All-Solid-State Lithium Batteries

FeS_(2)cathode is promising for all-solid-state lithium batteries due to its ultra-high capacity,low cost,and environmental friendliness.However,the poor performances,induced by limited electrode-electrolyte interface,severe volume expansion,and polysulfide shuttle,hinder the application of FeS_(2)in all-solid-state lithium batteries.Herein,an integrated 3D FeS_(2)electrode with full infiltration of Li6PS5Cl sulfide electrolytes is designed to address these challenges.Such a 3D integrated design not only achieves intimate and maximized interfacial contact between electrode and sulfide electrolytes,but also effectively buffers the inner volume change of FeS_(2)and completely eliminates the polysulfide shuttle through direct solid-solid conversion of Li2S/S.Besides,the vertical 3D arrays guarantee direct electron transport channels and horizontally shortened ion diffusion paths,endowing the integrated electrode with a remarkably reduced interfacial impedance and enhanced reaction kinetics.Benefiting from these synergies,the integrated all-solid-state lithium battery exhibits the largest reversible capacity(667 mAh g^(-1)),best rate performance,and highest capacity retention of 82%over 500 cycles at 0.1 C compared to both a liquid battery and non-integrated all-solid-state lithium battery.The cycling performance is among the best reported for FeS_(2)-based all-solid-state lithium batteries.This work presents an innovative synergistic strategy for designing long-cycling high-energy all-solid-state lithium batteries,which can be readily applied to other battery systems,such as lithium-sulfur batteries.

Integrated 3D Fan-out Package of RF Microsystem and Antenna for 5G Communications

A 3D fan-out packaging method for the integration of 5G communication RF microsystem and antenna is studied.First of all,through the double-sided wiring technology on the glass wafer,the fabrication of 5G antenna array is realized.Then the low power devices such as through silicon via(TSV)transfer chips,filters and antenna tuners are flip-welded on the glass wafer,and the glass wafer is reformed into a wafer permanently bonded with glass and resin by the injection molding process with resin material.Finally,the thinning resin surface leaks out of the TSV transfer chip,the rewiring is carried out on the resin surface,and then the power amplifier,low-noise amplifier,power management and other devices are flip-welded on the resin wafer surface.A ball grid array(BGA)is implanted to form the final package.The loss of the RF transmission line is measured by using the RF millimeter wave probe table.The results show that the RF transmission loss from the chip end to the antenna end in the fan-out package is very small,and it is only 0.26 dB/mm when working in 60 GHz.A slot coupling antenna is designed on the glass wafer.The antenna can operate at 60 GHz and the maximum gain can reach 6 dB within the working bandwidth.This demonstration successfully provides a feasible solution for the 3D fan-out integration of RF microsystem and antenna in 5G communications.

Collaborative Design in PDM / 3D CAD Integrated Environment

Some key issues in supporting collaborative design in product data management（PDM ） system and 3D computer aided design（CAD） system integrated environment are analyzed. The general architecture of the integrated environment is divided into five tiers and employs the transparently integrated mode, with the mode, function calling and information exchanging among independent PDM and CAD processes are carried out via message translation /parse approach. Product layout feature（PLF ） model definition is presented, PLF model is used to represent design intention at the preliminary design phase. The collaborative design methodology employing the PLF model in PDM/3D CAD integrated environment is analyzed. The design methodology can speed up the design process, reduce the investment and improve the product quality.

3D printing of osteocytic Dll4 integrated with PCL for cell fate determination towards osteoblasts in vitro

Since 3D printed hard materials could match the shape of bone,cell survival and fate determination towards osteoblasts in such materials have become a popular research target.In this study,a scaffold of hardmaterial for 3D fabrication was designed to regulate developmental signal(Notch)transduction guiding osteoblast differentiation.We established a polycaprolactone(PCL)and cell-integrated 3D printing system(PCI3D)to reciprocally print the beams of PCL and cell-laden hydrogel for a module.This PCI3D module holds good cell viability of over 87%,whereas cells show about sixfold proliferation in a 7-day culture.The osteocytic MLO-Y4 was engineered to overexpress Notch ligand Dll4,making up 25%after mixing with 75%stromal cells in the PCI3D module.Osteocytic Dll4,unlike other delta-like family members such as Dll1 or Dll3,promotes osteoblast differentiation and themineralization of primary mouse and a cell line of bone marrow stromal cells when cultured in a PCI3D module for up to 28 days.Mechanistically,osteocytic Dll4 could not promote osteogenic differentiation of the primary bone marrow stromal cells(BMSCs)after conditional deletion of the Notch transcription factor RBPjκby Cre recombinase.These data indicate that osteocytic Dll4 activates RBPjκ-dependent canonical Notch signaling in BMSCs for their oriented differentiation towards osteoblasts.Additionally,osteocytic Dll4 holds a great potential for angiogenesis in human umbilical vein endothelial cells within modules.Our study reveals that osteocytic Dll4 could be the osteogenic niche determining cell fate towards osteoblasts.This will open a new avenue to overcome the current limitation of poor cell viability and low bioactivity of traditional orthopedic implants.

Fabrication of polyetheretherketone(PEEK)-based 3D electronics with fine resolution by a hydrophobic treatment assisted hybrid additive manufacturing method

Additive manufacturing(AM)is a free-form technology that shows great potential in the integrated creation of three-dimensional(3D)electronics.However,the fabrication of 3D conformal circuits that fulfill the requirements of high service temperature,high conductivity and high resolution remains a challenge.In this paper,a hybrid AM method combining the fused deposition modeling(FDM)and hydrophobic treatment assisted laser activation metallization(LAM)was proposed for manufacturing the polyetheretherketone(PEEK)-based 3D electronics,by which the conformal copper patterns were deposited on the 3D-printed PEEK parts,and the adhesion between them reached the 5B high level.Moreover,the 3D components could support the thermal cycling test from-55℃ to 125℃ for more than 100 cycles.Particularly,the application of a hydrophobic coating on the FDM-printed PEEK before LAM can promote an ideal catalytic selectivity on its surface,not affected by the inevitable printing borders and pores in the FDM-printed parts,then making the resolution of the electroless plated copper lines improved significantly.In consequence,Cu lines with width and spacing of only60μm and 100μm were obtained on both as-printed and after-polished PEEK substrates.Finally,the potential of this technique to fabricate 3D conformal electronics was demonstrated.

Sourcing the merits of 3D integrated air cathodes for highperformance Zn-air batteries by bubble pump consumption chronoamperometry

Zn-air batteries(ZABs)as a potential energy conversion system suffer from low power density(typically≤200 mW·cm^(−2)).Recently,three-dimensional(3D)integrated air cathodes have demonstrated promising performance over traditional twodimensional(2D)plane ones,which is ascribed to enriched active sites and enhanced diffusion,but without experimental evidence.Herein,we applied a bubble pump consumption chronoamperometry(BPCC)method to quantitatively identify the gas diffusion coefficient(D)and effective catalytic sites density(ρEC)of the integrated air cathodes for ZABs.Furthermore,the D andρEC values can instruct consequent optimization on the growth of Co embedded N-doped carbon nanotubes(CoNCNTs)on carbon fiber paper(CFP)and aerophilicity tuning,giving 4 times D and 1.3 timesρEC over the conventional 2D Pt/C-CFP counterparts.As a result,using the CoNCNTs with half-wave potential of merely 0.78 V vs.RHE(Pt/C:0.89 V vs.RHE),the superaerophilic CoNCNTs-CFP cathode-based ZABs exhibited a superior peak power density of 245 mW·cm^(−2) over traditional 2D Pt/C-CFP counterparts,breaking the threshold of 200 mW·cm^(−2).This work reveals the intrinsic feature of the 3D integrated air cathodes by yielding exact D andρEC values,and demonstrates the feasibility of BPCC method for the optimization of integrated electrodes,bypassing trial-and-error strategy.

An optimal stacking order for mid-bond testing cost reduction of 3D IC

In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is built with the general consideration of both the test time for automatic test equipment(ATE)and manufacturing failure factors.An algorithm for testing cost and testing order optimization is proposed,and the minimum testing cost and optimized stacking order can be carried out by taking testing bandwidth and testing power as constraints.To prove the influence of the optimal stacking order on testing costs,two baselines stacked in sequential either in pyramid type or in inverted pyramid type are compared.Based on the benchmarks from ITC 02,experimental results show that for a 5-layer 3D IC,under different constraints,the optimal stacking order can reduce the test costs on average by 13%and 62%,respectively,compared to the pyramid type and inverted pyramid type.Furthermore,with the increase of the stack size,the test costs of the optimized stack order can be decreased.

Ultrahigh-power electrochemical double-layer capacitors based on structurally integrated 3D carbon tube arrays

The rational design of electrodes is the key to achieving ultrahigh-power performance in electrochemical energy storage devices.Recently,we have constructed well-organized and integrated three-dimensional(3D)carbon tube(CT)grids(3D-CTGs)using a 3D porous anodic aluminum oxide template-assisted method as electrodes of electrical double-layer capacitors(EDLCs),showing excellent frequency response performance.The unique design warrants fast ion migration channels,excellent electronic conductivity,and good structural stability.This study achieved one of the highest carbon-based ultrahigh-power EDLCs with the 3D-CTG electrodes,resulting in ultrahigh power of 437 and 1708 W·cm−3 with aqueous and organic electrolytes,respectively.Capacitors constructed with these electrodes would have important application prospects in the ultrahigh-power output.The rational design and fabrication of the 3D-CTGs electrodes have demonstrated their capability to build capacitors with ultrahighpower performance and open up new possibilities for applications requiring high-power output.

A ubiquitous knowledgeable data representation model(UKRM) for three-dimensional geographic information systems(3D GIS)

In the face of complicated, diversified three-dimensional world, the existing 3D GIS data models suffer from certain issues such as data incompatibility, insufficiency in data representation and representation types, among others. It is often hard to meet the requirements of multiple application purposes(users) related to GIS spatial data management and data query and analysis, especially in the case of massive spatial objects. In this study, according to the habits of human thinking and recognition, discrete expressions(such as discrete curved surface(DCS), and discrete body(DB)) were integrated and two novel representation types(including function structure and mapping structure) were put forward. A flexible and extensible ubiquitous knowledgeable data representation model(UKRM) was then constructed, in which structurally heterogeneous multiple expressions(including boundary representation(B-rep), constructive solid geometry(CSG), functional/parameter representation, etc.) were normalized. GIS's ability in representing the massive, complicated and diversified 3D world was thus greatly enhanced. In addition, data reuse was realized, and the bridge linking static GIS to dynamic GIS was built up. Primary experimental results illustrated that UKRM was overwhelmingly superior to the current data models(e.g. IFC, City GML) in describing both regular and irregular spatial objects.

Monolithic three-dimensional integration of aligned carbon nanotube transistors for high-performance integrated circuits

Carbon nanotube field-effect transistors(CNT FETs)have been demonstrated to exhibit high performance only through low-temperature fabrication process and require a low thermal budget to construct monolithic three-dimensional(M3D)integrated circuits(ICs),which have been considered a promising tech-nology to meet the demands of high-bandwidth computing and fully func-tional integration.However,the lack of high-quality CNT materials at the upper layer and a low-parasitic interlayer dielectric(ILD)makes the reported M3D CNT FETs and ICs unable to provide the predicted high performance.In this work,we demonstrate a multilayer stackable process for M3D integration of high-performance aligned carbon nanotube(A-CNT)transistors and ICs.A low-κ(-3)interlayer SiO_(2)layer is prepared from spin-on-glass(SOG)through processes with a highest temperature of 220℃,presenting low parasitic capaci-tance between two transistor layers and excellent planarization to offer an ideal surface for the A-CNT and device fabrication process.A high-quality A-CNT film with a carrier mobility of 650 cm 2 V^(-1)s^(-1)is prepared on the ILD layer through a clean transfer process,enabling the upper CNT FETs fabri-cated with a low-temperature process to exhibit high on-state current(1 mAμm^(-1))and peak transconductance(0.98 mSμm^(-1)).The bottom A-CNT FETs maintain pristine high performance after undergoing the ILD growth and upper FET fabrication.As a result,5-stage ring oscillators utilizing the M3D architecture show a gate propagation delay of 17 ps and an active region of approximately 100μm 2,representing the fastest and the most compact M3D ICs to date.

AIR-GAP-BASED RF COAXIAL TSV AND ITS CHARACTERISTIC ANALYSIS

Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via （TSV） with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab, for such RF applications. Firstly, the detailed fabrication process is described to explain how to acquire such a structure. Then, an Resistor Inductance Conductance Capacitance （RLGC） model is developed to profile the transverse electromagnetic field effect of the proposed air-gap TSV. The model is further verified by a 3D field solver program through the S-parameter comparison. With reference to the numerically simulated results, this analytical model delivers a maximum deviation of less than 6%0, on the conditions of varying diameters, outer to inner radius ratios, and SU-8 central angles, etc. Taking advantages of scalability of the model, a number of air-gap-based TSV designs are simulated, providing 1.6-4.0 times higher bandwidth than the con- ventional coaxial TSVs and leading to an efficient high frequency vertical RF interconnection solution for 3D ICs.

Electrical characterization of integrated passive devices using thin film technology for 3D integration

With the development of 3D integration technology, microsystems with vertical interconnects are attracting attention from researchers and industry applications. Basic elements of integrated passive devices （IPDs）, including inductors, capacitors, and resistors, could dramatically save the tbotprint of the system, optimize the form factor, and improve the performance of radio frequency （RF） systems. In this paper, IPDs using thin film built-up technology are introduced, and the design and characterization of coplanar waveguides （CPWs）, inductors, and capacitors are presented.

Resistive switching memory for high density storage and computing

The resistive random access memory(RRAM)has stimulated a variety of promising applications including programmable analog circuit,massive data storage,neuromorphic computing,etc.These new emerging applications have huge demands on high integration density and low power consumption.The cross-point configuration or passive array,which offers the smallest footprint of cell size and feasible capability of multi-layer stacking,has received broad attention from the research community.In such array,correct operation of reading and writing on a cell relies on effective elimination of the sneaking current coming from the neighboring cells.This target requires nonlinear I-V characteristics of the memory cell,which can be realized by either adding separate selector or developing implicit build-in nonlinear cells.The performance of a passive array largely depends on the cell nonlinearity,reliability,on/off ratio,line resistance,thermal coupling,etc.This article provides a comprehensive review on the progress achieved concerning 3D RRAM integration.First,the authors start with a brief overview of the associative problems in passive array and the category of 3D architectures.Next,the state of the arts on the development of various selector devices and self-selective cells are presented.Key parameters that influence the device nonlinearity and current density are outlined according to the corresponding working principles.Then,the reliability issues in 3D array are summarized in terms of uniformity,endurance,retention,and disturbance.Subsequently,scaling issue and thermal crosstalk in 3D memory array are thoroughly discussed,and applications of 3D RRAM beyond storage,such as neuromorphic computing and CMOL circuit are discussed later.Summary and outlooks are given in the final.

Development of a viable 3D integrated circuit technology

Three-dimensional integrated circuit technology with transistors stacked on top of one an-other in multi-layer silicon film has always been a vision in the future technology direction. While the idea is simple, the technique to obtain high performance multi-layer transistors is extraordinarily diffi-cult. Not until recently does such technology become feasible. In this paper, the background and vari-ous techniques to form three-dimensional circuits will be reviewed. Recent development of a simple and promising technology to achieve three-dimensional integration using Metal-Induced-Lateral-Crystalliza-tion will be described. Preliminary results of 3D inverters will also be provided to demonstrate the viabil-ity for 3D integration.

Thermal reliability analysis and optimization of polymer insulating through-silicon-vias(TSVs) for 3D integration

Polymer insulating through-silicon-vias （TSVs） is an attractive approach for high-performance 3D integration systems. To further demonstrate the polymer insulating TSVs, this paper investigates the thermal stability by measuring the leakage current under bias-temperature condition, studies the thermal stress characteristics with Finite Element Analysis （FEA）, and tries to improve the thermal mechanical reliability of high-density TSVs array by optimizing the geometry parameters of pitch, liner and redistribution layer （RDL）. The electrical measurements show the polymer insulating TSVs can maintain good insulation capability （less than 2x 10TM A） under challenging bias-temperature conditions of 20 V and 200~C, despite the leakage degra- dation observation. The FEA results show that the thermal stress is significantly reduced at the sidewall, but highly concen- trates at the surface, which is the potential location of mechanical failure. And, the analysis results indicate that the polymer insulating TSVs （diameter of 10 μm, depth of 50 μm） array with a pitch of 20 μm, liner thickness of 1 μm and RDL radius of 9 μm has an optimized thermal-mechanical reliability for application.

Impedance matching for the reduction of signal reflection in high speed multilevel three-dimensional integrated chips

In high speed three-dimensional integrated circuits （3D ICs）, through silicon via （TSV） insertion causes impedance discontinuities along the interconnect-TSV channel that results in signal reflection. As demonstrated for a two-plane interconnect structure connected by a TSV, we incorporate an appropriate capacitance at the junction to mitigate the signal reflection with gigascale frequencies. Based on 65 nm technology and S-parameter analysis, the decrease of signal reflection can be 189% at the tuned frequency of 5 GHz. Extending this method to the five-plane interconnect structure further, the reduction of signal reflection can achieve 400%. So we could broaden this method to any multilevel 3D interconnect structures. This method can also be applied to a circuit with tunable operating frequencies by digitally connecting the corresponding matching capacitance into the circuit through switches. There are remarkable improvements of the quality of the transmitting signals.

Inkjet printing technology for increasing the I/O density of 3D TSV interposers

Interposers with through-silicon vias(TSVs)play a key role in the three-dimensional integration and packaging of integrated circuits and microelectromechanical systems.In the current practice of fabricating interposers,solder balls are placed next to the vias;however,this approach requires a large foot print for the input/output(I/O)connections.Therefore,in this study,we investigate the possibility of placing the solder balls directly on top of the vias,thereby enabling a smaller pitch between the solder balls and an increased density of the I/O connections.To reach this goal,inkjet printing(that is,piezo and super inkjet)was used to successfully fill and planarize hollow metal TSVs with a dielectric polymer.The under bump metallization(UBM)pads were also successfully printed with inkjet technology on top of the polymer-filled vias,using either Ag or Au inks.The reliability of the TSV interposers was investigated by a temperature cycling stress test(−40℃ to+125℃).The stress test showed no impact on DC resistance of the TSVs;however,shrinkage and delamination of the polymer was observed,along with some micro-cracks in the UBM pads.For proof of concept,SnAgCu-based solder balls were jetted on the UBM pads.

Design of a 3D Wilkinson power divider using through glass via technology

Due to its low electrical loss and low process cost, a glass interposer has been developed to provide a compelling alternative to the silicon-based interposer for packaging of future 2-D and 3-D ICs. In this study,through glass vias(TGVs) are used to implement 3-D inductors for minimal footprint and large quality factor. Using the inductors and parallel plate capacitors, a compact 3-D Wilkinson power divider is designed and analyzed.Compared with some reported power dividers, the proposed TGV-based circuit has an ultra-compact size and excellent electrical performance.

Analysis and optimization of TSV–TSV coupling in three-dimensional integrated circuits

Through silicon via （TSV）-TSV coupling is detrimental to the performance of three-dimensional （3D） integrated circuits （ICs） with the major negative effect of introducing coupling noise. In order to obtain an accurate estimation of the coupling level from TSV-TSV in the early design stage, this paper first proposes an impedance- level model of the coupling channel between TSVs based on a two-port network, and then derives the formula of the coupling coefficient to describe the TSV-TSV coupling effect. The accuracy of the formula is validated by comparing the results with 3D full-wave simulations. Furthermore, a design technique for optimizing the coupling between adjacent coupled signal TSVs is proposed. Through SPICE simulations, the proposed technique shows its feasibility to reduce the coupling noise for both a simple TSV-TSV circuit and a complicated circuit with more TSVs, and demonstrates its potential for designers in achieving the goal of improving the electrical pertbrmance of3D ICs.

Circuit modeling and performance analysis of SWCNT bundle 3D interconnects

Metallic carbon nanotubes （CNTs） have been proposed as a promising alternative to Cu interconnects in future integrated circuits （ICs） for their remarkable conductive, mechanical and thermal properties. Compact equiv alent circuit models for single-walled carbon nanotube （SWCNT） bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional （3D） ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respec tively.