高阻断电压、大功率密度、高转化效率是电力电子器件技术持续追求的目标,基于4H-SiC优异的材料特性,在电力电子器件应用方面具有广阔的发展前景。围绕SiC MOSFET器件对外延材料的需求,介绍了国内外主流的SiC外延设备及国产SiC衬底的发展...高阻断电压、大功率密度、高转化效率是电力电子器件技术持续追求的目标,基于4H-SiC优异的材料特性,在电力电子器件应用方面具有广阔的发展前景。围绕SiC MOSFET器件对外延材料的需求,介绍了国内外主流的SiC外延设备及国产SiC衬底的发展,并重点介绍了宽禁带半导体电力电子器件国家重点实验室在国产150 mm(6英寸)SiC衬底上的高速外延技术进展。通过关键技术攻关,实现了150 mm SiC外延材料表面缺陷密度≤0.5 cm-2,BPD缺陷密度≤0.1 cm-2,片内掺杂浓度不均匀性≤5%,片内厚度不均匀性≤1%。基于自主外延材料,实现了650~1200 V SiC MOSFET产品商业化以及6.5~15 kV高压SiC MOSFET器件的产品定型。展开更多
The high-temperature performance of 4H-SiC ultraviolet avalanche photodiodes(APDs)in both linear and Geiger modes is extensively investigated.During the temperature-dependent measurements,a fixed bias voltage is adopt...The high-temperature performance of 4H-SiC ultraviolet avalanche photodiodes(APDs)in both linear and Geiger modes is extensively investigated.During the temperature-dependent measurements,a fixed bias voltage is adopted for the device samples,which is much more practical and important for high-temperature applications.The results show that the fabricated 4H-SiC APDs are very stable and reliable at high temperatures.As the temperature increases from room temperature to 425 K,the dark current at 95%of the breakdown voltage increases slightly and remains lower than40 pA.In Geiger mode,our 4H-SiC APDs can be self-quenched in a passive-quenching circuit,which is expected for highspeed detection systems.Moreover,an interesting phenomenon is observed for the first time:the single-photon detection efficiency shows a non-monotonic variation as a function of temperature.The physical mechanism of the variation in hightemperature performance is further analyzed.The results in this work can provide a fundamental reference for researchers in the field of 4H-SiC APD ultraviolet detectors.展开更多
Thermal oxidation and hydrogen annealing were applied on a 100μm thick Al-doped p-type 4H-Si C epitaxial wafer to modulate the minority carrier lifetime,which was investigated by microwave photoconductive decay(μ-PC...Thermal oxidation and hydrogen annealing were applied on a 100μm thick Al-doped p-type 4H-Si C epitaxial wafer to modulate the minority carrier lifetime,which was investigated by microwave photoconductive decay(μ-PCD).The minority carrier lifetime decreased after each thermal oxidation.On the contrary,with the hydrogen annealing time increasing to3 hours,the minority carrier lifetime increased from 1.1μs(as-grown)to 3.14μs and then saturated after the annealing time reached 4 hours.The increase of surface roughness from 0.236 nm to 0.316 nm may also be one of the reasons for limiting the further improvement of the minority carrier lifetimes.Moreover,the whole wafer mappings of minority carrier lifetimes before and after hydrogen annealing were measured and discussed.The average minority carrier lifetime was up to 1.94μs and non-uniformity of carrier lifetime reached 38%after 4-hour hydrogen annealing.The increasing minority carrier lifetimes could be attributed to the double mechanisms of excess carbon atoms diffusion caused by selective etching of Si atoms and passivation of deep-level defects by hydrogen atoms.展开更多
A silicon (Si)/silicon carbide (4H-SiC) heterojunction double-trench metal-oxide-semiconductor field effect transistor (MOSFET) (HDT-MOS) with the gate-controlled tunneling effect is proposed for the first time based ...A silicon (Si)/silicon carbide (4H-SiC) heterojunction double-trench metal-oxide-semiconductor field effect transistor (MOSFET) (HDT-MOS) with the gate-controlled tunneling effect is proposed for the first time based on simulations. In this structure, the channel regions are made of Si to take advantage of its high channel mobility and carrier density. The voltage-withstanding region is made of 4H-SiC so that HDT-MOS has a high breakdown voltage (BV) similar to pure 4H-SiC double-trench MOSFETs (DT-MOSs). The gate-controlled tunneling effect indicates that the gate voltage (V_(G)) has a remarkable influence on the tunneling current of the heterojunction. The accumulation layer formed with positive VG can reduce the width of the Si/SiC heterointerface barrier, similar to the heavily doped region in an Ohmic contact. This narrower barrier is easier for electrons to tunnel through, resulting in a lower heterointerface resistance. Thus, with similar BV (approximately 1770 V), the specific on-state resistance (R_(ON-SP)) of HDT-MOS is reduced by 0.77 mΩ·cm^(2) compared with that of DT-MOS. The gate-to-drain charge (Q_(GD)) and switching loss of HDT-MOS are 52.14% and 22.59% lower than those of DT-MOS, respectively, due to the lower gate platform voltage (V_(GP)) and the corresponding smaller variation (ΔV_(GP)). The figure of merit (Q_(GD)×R_(ON-SP)) of HDT-MOS decreases by 61.25%. Moreover, the heterointerface charges can reduce RON-SP of HDT-MOS due to trap-assisted tunneling while the heterointerface traps show the opposite effect. Therefore, the HDT-MOS structure can significantly reduce the working loss of SiC MOSFET, leading to a lower temperature rise when the devices are applied in the system.展开更多
High-k materials as an alternative dielectric layer for SiC power devices have the potential to reduce interfacial state defects and improve MOS channel conduction capability.Besides,under identical conditions of gate...High-k materials as an alternative dielectric layer for SiC power devices have the potential to reduce interfacial state defects and improve MOS channel conduction capability.Besides,under identical conditions of gate oxide thickness and gate voltage,the high-k dielectric enables a greater charge accumulation in the channel region,resulting in a larger number of free electrons available for conduction.However,the lower energy band gap of high-k materials leads to significant leakage currents at the interface with Si C,which greatly affects device reliability.By inserting a layer of SiO_(2)between the high-k material and Si C,the interfacial barrier can be effectively widened and hence the leakage current will be reduced.In this study,the optimal thickness of the intercalated SiO_(2)was determined by investigating and analyzing the gate dielectric breakdown voltage and interfacial defects of a dielectric stack composed of atomic-layer-deposited Al_(2)O_(3)layer and thermally nitride SiO_(2).Current-voltage and high-frequency capacitance-voltage measurements were performed on metal-oxide-semiconductor test structures with 35 nm thick Al_(2)O_(3)stacked on 1 nm,2 nm,3 nm,6 nm,or 9 nm thick nitride SiO_(2).Measurement results indicated that the current conducted through the oxides was affected by the thickness of the nitride oxide and the applied electric field.Finally,a saturation thickness of stacked SiO_(2)that contributed to dielectric breakdown and interfacial band offsets was identified.The findings in this paper provide a guideline for the SiC gate dielectric stack design with the breakdown strength and the interfacial state defects considered.展开更多
采用数值模拟研究PVT法φ150 mm 4H-SiC单晶生长的功率、频率选择、坩埚位置及保温厚度等关键生长参数。研究表明φ150 mm 4H-SiC单晶生长功率是2inch 4H-SiC生长功率的2倍,优化的加热频率在5 k Hz以下,系统分析不同生长参数下生长腔内...采用数值模拟研究PVT法φ150 mm 4H-SiC单晶生长的功率、频率选择、坩埚位置及保温厚度等关键生长参数。研究表明φ150 mm 4H-SiC单晶生长功率是2inch 4H-SiC生长功率的2倍,优化的加热频率在5 k Hz以下,系统分析不同生长参数下生长腔内径向及轴向温度梯度的变化规律。在此基础上初步的进行了φ150 mm 4H-SiC单晶的生长工作,获得了无裂纹、直径完整的高质量SiC衬底材料。拉曼光谱Mapping测量显示φ150 mm SiC衬底全片无多型,均为4H-SiC晶型。X光摇摆曲线显示半宽小于30 arcsec。采用掺杂过渡金属V杂质,获得了电阻率超过5×109Ω·cm的150 mm SiC衬底。展开更多
文摘高阻断电压、大功率密度、高转化效率是电力电子器件技术持续追求的目标,基于4H-SiC优异的材料特性,在电力电子器件应用方面具有广阔的发展前景。围绕SiC MOSFET器件对外延材料的需求,介绍了国内外主流的SiC外延设备及国产SiC衬底的发展,并重点介绍了宽禁带半导体电力电子器件国家重点实验室在国产150 mm(6英寸)SiC衬底上的高速外延技术进展。通过关键技术攻关,实现了150 mm SiC外延材料表面缺陷密度≤0.5 cm-2,BPD缺陷密度≤0.1 cm-2,片内掺杂浓度不均匀性≤5%,片内厚度不均匀性≤1%。基于自主外延材料,实现了650~1200 V SiC MOSFET产品商业化以及6.5~15 kV高压SiC MOSFET器件的产品定型。
基金the National Natural Science Foundation of China(Grant No.61974134)Hebei Province Outstanding Youth Fund(Grant No.F2021516001).
文摘The high-temperature performance of 4H-SiC ultraviolet avalanche photodiodes(APDs)in both linear and Geiger modes is extensively investigated.During the temperature-dependent measurements,a fixed bias voltage is adopted for the device samples,which is much more practical and important for high-temperature applications.The results show that the fabricated 4H-SiC APDs are very stable and reliable at high temperatures.As the temperature increases from room temperature to 425 K,the dark current at 95%of the breakdown voltage increases slightly and remains lower than40 pA.In Geiger mode,our 4H-SiC APDs can be self-quenched in a passive-quenching circuit,which is expected for highspeed detection systems.Moreover,an interesting phenomenon is observed for the first time:the single-photon detection efficiency shows a non-monotonic variation as a function of temperature.The physical mechanism of the variation in hightemperature performance is further analyzed.The results in this work can provide a fundamental reference for researchers in the field of 4H-SiC APD ultraviolet detectors.
基金Project supported by Key Area Research and Development Project of Guangdong Province,China(Grant No.2020B010170002)the Science Challenge Project(Grant No.TZ2018003-1-101)+4 种基金the Natural Science Foundation of Fujian Province of China for Distinguished Young Scholars(Grant No.2020J06002)the Science and Technology Project of Fujian Province of China(Grant No.2020I0001)the Fundamental Research Funds for the Central Universities(Grant Nos.20720190049 and 20720190053)the Science and Technology Key Projects of Xiamen(Grant No.3502ZCQ20191001)the National Natural Science Foundation of China(Grant No.51871189)。
文摘Thermal oxidation and hydrogen annealing were applied on a 100μm thick Al-doped p-type 4H-Si C epitaxial wafer to modulate the minority carrier lifetime,which was investigated by microwave photoconductive decay(μ-PCD).The minority carrier lifetime decreased after each thermal oxidation.On the contrary,with the hydrogen annealing time increasing to3 hours,the minority carrier lifetime increased from 1.1μs(as-grown)to 3.14μs and then saturated after the annealing time reached 4 hours.The increase of surface roughness from 0.236 nm to 0.316 nm may also be one of the reasons for limiting the further improvement of the minority carrier lifetimes.Moreover,the whole wafer mappings of minority carrier lifetimes before and after hydrogen annealing were measured and discussed.The average minority carrier lifetime was up to 1.94μs and non-uniformity of carrier lifetime reached 38%after 4-hour hydrogen annealing.The increasing minority carrier lifetimes could be attributed to the double mechanisms of excess carbon atoms diffusion caused by selective etching of Si atoms and passivation of deep-level defects by hydrogen atoms.
基金the Major Science and Technology Program of Anhui Province under Grant No.2020b05050007.
文摘A silicon (Si)/silicon carbide (4H-SiC) heterojunction double-trench metal-oxide-semiconductor field effect transistor (MOSFET) (HDT-MOS) with the gate-controlled tunneling effect is proposed for the first time based on simulations. In this structure, the channel regions are made of Si to take advantage of its high channel mobility and carrier density. The voltage-withstanding region is made of 4H-SiC so that HDT-MOS has a high breakdown voltage (BV) similar to pure 4H-SiC double-trench MOSFETs (DT-MOSs). The gate-controlled tunneling effect indicates that the gate voltage (V_(G)) has a remarkable influence on the tunneling current of the heterojunction. The accumulation layer formed with positive VG can reduce the width of the Si/SiC heterointerface barrier, similar to the heavily doped region in an Ohmic contact. This narrower barrier is easier for electrons to tunnel through, resulting in a lower heterointerface resistance. Thus, with similar BV (approximately 1770 V), the specific on-state resistance (R_(ON-SP)) of HDT-MOS is reduced by 0.77 mΩ·cm^(2) compared with that of DT-MOS. The gate-to-drain charge (Q_(GD)) and switching loss of HDT-MOS are 52.14% and 22.59% lower than those of DT-MOS, respectively, due to the lower gate platform voltage (V_(GP)) and the corresponding smaller variation (ΔV_(GP)). The figure of merit (Q_(GD)×R_(ON-SP)) of HDT-MOS decreases by 61.25%. Moreover, the heterointerface charges can reduce RON-SP of HDT-MOS due to trap-assisted tunneling while the heterointerface traps show the opposite effect. Therefore, the HDT-MOS structure can significantly reduce the working loss of SiC MOSFET, leading to a lower temperature rise when the devices are applied in the system.
基金Project supported by the Key Area Research and Development Program of Guangdong Province of China(Grant No.2021B0101300005)the National Key Research and Development Program of China(Grant No.2021YFB3401603)。
文摘High-k materials as an alternative dielectric layer for SiC power devices have the potential to reduce interfacial state defects and improve MOS channel conduction capability.Besides,under identical conditions of gate oxide thickness and gate voltage,the high-k dielectric enables a greater charge accumulation in the channel region,resulting in a larger number of free electrons available for conduction.However,the lower energy band gap of high-k materials leads to significant leakage currents at the interface with Si C,which greatly affects device reliability.By inserting a layer of SiO_(2)between the high-k material and Si C,the interfacial barrier can be effectively widened and hence the leakage current will be reduced.In this study,the optimal thickness of the intercalated SiO_(2)was determined by investigating and analyzing the gate dielectric breakdown voltage and interfacial defects of a dielectric stack composed of atomic-layer-deposited Al_(2)O_(3)layer and thermally nitride SiO_(2).Current-voltage and high-frequency capacitance-voltage measurements were performed on metal-oxide-semiconductor test structures with 35 nm thick Al_(2)O_(3)stacked on 1 nm,2 nm,3 nm,6 nm,or 9 nm thick nitride SiO_(2).Measurement results indicated that the current conducted through the oxides was affected by the thickness of the nitride oxide and the applied electric field.Finally,a saturation thickness of stacked SiO_(2)that contributed to dielectric breakdown and interfacial band offsets was identified.The findings in this paper provide a guideline for the SiC gate dielectric stack design with the breakdown strength and the interfacial state defects considered.
文摘采用数值模拟研究PVT法φ150 mm 4H-SiC单晶生长的功率、频率选择、坩埚位置及保温厚度等关键生长参数。研究表明φ150 mm 4H-SiC单晶生长功率是2inch 4H-SiC生长功率的2倍,优化的加热频率在5 k Hz以下,系统分析不同生长参数下生长腔内径向及轴向温度梯度的变化规律。在此基础上初步的进行了φ150 mm 4H-SiC单晶的生长工作,获得了无裂纹、直径完整的高质量SiC衬底材料。拉曼光谱Mapping测量显示φ150 mm SiC衬底全片无多型,均为4H-SiC晶型。X光摇摆曲线显示半宽小于30 arcsec。采用掺杂过渡金属V杂质,获得了电阻率超过5×109Ω·cm的150 mm SiC衬底。
