Effect of surface roughness on femtosecond laser ablation of 4H-SiC substrates

Ablation threshold is an important concept in the study of femtosecond laser micro-and nano-machining.In this paper,the ablation experiments of three kinds of surface roughness 4H-Si C substrates irradiated by femtosecond laser were carried out.The feature thresholds were systematically measured for three surface roughness Si C substrates and found in the modification and annealing regions ranging from coincidence(R_(a)=0.5 nm)to a clear demarcation(R_(a)=5.5 nm),eventually being difficult to identify the presence of the former(R_(a)=89 nm).Under multi-pulse laser irradiation,oriented ripple structures were generated in the annealing region,where deep subwavelength ripples(about 110 nm,Λ≈0.2λ)can be generated above substrates with surface roughness higher than 5.5 nm.We investigated the effect of surface roughness on the ablation morphology,ablation threshold,and periodic structures of femtosecond laser ablation of 4H-Si C substrates,while the ablation threshold was tended to decrease and stabilize with the increase of pulse number N≥500.

真空慢退火工艺对4H-SiC核辐射探测器性能的影响

制备了一种肖特基二极管结构的4H-SiC辐射探测器.在真空环境下,用不同的温度对欧姆电极进行慢退火处理,达到良好的欧姆接触.对其反向I-V特性和能量分辨率进行测试对比,欧姆电极在800℃条件下性能最好,在全耗尽状态下能量分辨率为1.36%,耐压测试运行稳定, 200 V偏压下漏电流仅有463 pA.与其他退火温度相比,该工艺下的4H-SiC探测器运行稳定,具有漏电流低、能量分辨率高的优势.

电子辐照对4H-SiC MOS材料缺陷的影响

4H-SiC金属氧化物半导体(MOS)基器件在电子辐照环境下应用时可能产生新的材料缺陷,导致其电学性能发生退化。本文选取结构最简单的MOS基器件(4H-SiC MOS电容器)为对象,研究了一系列电子辐照剂量下材料缺陷的演变情况。在10 MeV电子束下对MOS样品进行30、50、100、500、1 000 kGy剂量的辐照,对辐照前、后样品进行深能级瞬态谱测试(DLTS)和电容-电压(C-V)曲线表征。DLTS实验结果表明,低剂量电子辐照前、后4H-SiC/SiO_(2)界面及近界面处的缺陷没有发生明显变化,而高剂量辐照导致双碳间隙原子缺陷的构型发生了改变,演变后的构型能级位置更深,化学结构更加稳定。C-V曲线测试结果发现,不同电子辐照剂量导致MOS电容器平带电压发生不同程度的负向漂移,这很可能是SiO_(2)氧化层中氧空位数量和4H-SiC/SiO_(2)界面及近界面处缺陷数量共同影响的结果。本文研究结果对研发和优化抗电子辐照的4H-SiC MOS制备工艺具有一定的参考价值。

基于4H-SiC的开槽四梁式压阻式加速度计设计及仿真研究

基于4H-SiC设计了一种开槽四梁式的压阻式加速度计,通过分析开槽位置、开槽大小对传感器灵敏度及固有频率的影响确定了开槽的相关参数,并对该结构采用有限元方法进行了热-力耦合仿真,确定了该结构在不同温度场下施加不同载荷时的理论电压输出。研究结果表明:该结构相较于传统双端四梁结构输出灵敏度提升51.4%,固有频率仅下降14.2%,在ANSYS 600℃的稳态温度场环境下,传感器输入载荷与输出电压成线性关系,理论满量程输出为39.71 mV。

基于4H-SiC的低横向灵敏度压阻式加速度计设计仿真研究

文中基于4H-SiC设计了一种开槽式低横向灵敏度压阻式加速度计,通过分析支撑梁位置及开槽尺寸对加速度计性能的影响确定了相关结构参数,并对该结构采用有限元方法进行了热-力耦合仿真,确定了该结构在600℃温度场中施加不同载荷时的理论电压输出。研究结果表明:该结构相较于已有的双端四梁结构X轴方向的横向灵敏度由3.3%降至2.6%,Y轴方向横向灵敏度由29.9%降至1.5%,传感器芯片在600℃高温环境下输入载荷与输出电压呈线性关系,100 g载荷下的理论输出电压为3.65 mV。

4H-SiC晶片热导率的激光拉曼光谱研究

在本研究中,使用激光激发的激光拉曼光谱研究了4H-SiC晶片从低温(80 K)到室温(290 K)的热导率。在整个测量过程中,激光既作为拉曼光谱的激发源又作为热源,通过激光加热提高了晶片表面的局部温度。同样,拉曼峰的位置会随着晶片温度的升高而向高频侧偏移,通过分析拉曼光谱位置的偏移和局部温度升高的关系得到了4H-SiC晶片的热导率。结果表明,4H-SiC晶片的热导率在低温情况下随温度升高而升高,此时K∝T 3,当热导率的值达到最大后随着温度的升高而降低,此时K∝T-1,这归因于声子-声子间相互作用和声子缺陷散射的作用。

4H-SiC光导开关性能的仿真研究

碳化硅光导开关是相关领域的研究热点,但是文献中对4H-SiC光导开关的理论研究仍然以集总元件模型为主,仅能给出定性结果,典型文献中瞬态条件下的实验数据还没有定量的理论解释。文章使用SilvacoTCAD软件中的器件-电路混合模式,结合自编的载流子迁移率接口程序,对4H-SiC光导开关的光学电学特性进行模拟仿真。单脉冲响应的仿真结果表明,器件在瞬态条件下的峰值光电流随光能的变化与文献中的实验数据相符合,表明所用模型和参数具有合理性。对影响单脉冲响应的主要因素,包括脉冲能量、脉冲宽度、碳化硅厚度,进行了计算和分析。同时,针对两种碳化硅厚度的器件,进行了多脉冲串响应的计算和分析。文章得到的结果和结论对碳化硅光导开关的进一步研究具有较好的参考价值。

Defects evolution in n-type 4H-SiC induced by electron irradiation and annealing

Radiation damage produced in 4H-SiC by electrons of different doses is presented by using multiple characterization techniques. Raman spectra results indicate that SiC crystal structures are essentially impervious to 10 Me V electron irradiation with doses up to 3000 kGy. However, irradiation indeed leads to the generation of various defects, which are evaluated through photoluminescence(PL) and deep level transient spectroscopy(DLTS). The PL spectra feature a prominent broad band centered at 500 nm, accompanied by several smaller peaks ranging from 660 to 808 nm. The intensity of each PL peak demonstrates a linear correlation with the irradiation dose, indicating a proportional increase in defect concentration during irradiation. The DLTS spectra reveal several thermally unstable and stable defects that exhibit similarities at low irradiation doses.Notably, after irradiating at the higher dose of 1000 kGy, a new stable defect labeled as R_(2)(Ec-0.51 eV) appeared after annealing at 800 K. Furthermore, the impact of irradiation-induced defects on SiC junction barrier Schottky diodes is discussed. It is observed that high-dose electron irradiation converts SiC n-epilayers to semi-insulating layers. However, subjecting the samples to a temperature of only 800 K results in a significant reduction in resistance due to the annealing out of unstable defects.

基于4H-SiC探测器多球谱仪的聚变中子能谱测量研究

Bonner多球谱仪作为主要用于测量中子能谱和剂量的仪器,对于聚变装置的辐射监测与防护具有重要意义。为了研究超导托卡马克(Experimental Advanced Superconducting Tokamak,EAST)在中性束注入(Neutral Beam Injector,NBI)加热实验条件下的中子能谱和剂量当量,研制了一套由涂有6LiF的4H-SiC半导体探测器和8个慢化球组成的Bonner中子多球谱仪,在相应放电实验中进行了实验测量。通过与EAST上中子注量监测结果进行源强归一化处理,并结合模拟计算获得的每个慢化球中子响应函数,利用最大熵程序解算出大厅内部中子能谱分布。进一步通过中子注量-剂量转化系数获得中子剂量当量,并与蒙特卡罗方法模拟计算的主机大厅内相应位置的中子能谱和剂量当量进行比较,归一化聚变中子源项下测量位置的中子注量与模拟值的比值为0.98;归一化聚变中子源项下测量位置的周围剂量当量与模拟值的比值为1.05。对比结果验证了该多球谱仪在EAST装置上初步应用的可靠性。

1000V 4H-SiC VDMOS结构设计与特性研究

设计并优化了一种基于4H-SiC的1000V垂直双扩散金属氧化物半导体场效应晶体管(VDMOS),在留有50%的裕度后,通过Silvaco仿真软件详细研究了器件各项参数与耐压特性之间的关系。经优化,器件的阈值电压为2.3V,击穿电压达1525V,相较于相同耐压条件下的Si基VDMOS,4H-SiC VDMOS的击穿电压提升了12%。此外,击穿时4H-SiC VDMOS表面电场分布相对均匀,最大值为3.4×10^(6)V/cm。终端有效长度为15μm,约为Si基VDMOS的6%,总体面积减小了近1/10。并且4H-SiC VDMOS结构简单,与相同耐压条件下的Si基VDMOS相比,未增加额外的工艺步骤,易于实现。

Molecular dynamics simulation of the material removal in the scratching of 4H-SiC and 6H-SiC substrates

Single crystal silicon carbide(SiC)is widely used for optoelectronics applications.Due to the anisotropic characteristics of single crystal materials,the C face and Si face of single crystal SiC have different physical properties,which may fit for particular application purposes.This paper presents an investigation of the material removal and associated subsurface defects in a set of scratching tests on the C face and Si face of 4H-SiC and 6H-SiC materials using molecular dynamics simulations.The investigation reveals that the sample material deformation consists of plastic,amorphous transformations and dislocation slips that may be prone to brittle split.The results showed that the material removal at the C face is more effective with less amorphous deformation than that at the Si face.Such a phenomenon in scratching relates to the dislocations on the basal plane(0001)of the SiC crystal.Subsurface defects were reduced by applying scratching cut depths equal to integer multiples of a half molecular lattice thickness,which formed a foundation for selecting machining control parameters for the best surface quality.

Thermo-Mechanical Simulation of Self-Heating of a High-Power Diode Made of Ti_(3)SiC_(2)(MAX) Phase-on-4H-SiC Substrate

The fact that traditional semiconductors have almost reached their performance limits in high power applications,is leading to failure in high power devices.This failure results from self-heating effects,leading to higher temperature and a breakdown of the electrical contact.The good thermal and mechanical properties of 4 H-SiC and Ti_(3)SiC_(2) and their good performance at high temperatures make them good candidates for high power applications.In order to improve the performance of electrical contacts,a thermo-mechanical simulation was carried out using the finite element method to study the self-heating effects in a high power PN diode made of a 4 H-SiC substrate with a Ti_(3)SiC_(2) electrical contact and Al_(3)Ti metallization.The three-dimensional model took into account the temperature dependency of several thermal and mechanical properties of the different materials to improve calculation accuracy.To simulate the self-heating,the power loss in the diode was calculated from the corresponding direct I-V characteristic.In addition,the interfacial thermal resistances(ITR)between the different layers were varied and studied in the thermo-mechanical investigation,in sequence to determine their effects on the heat dissipation and the resulting stresses in the model.The results show that for realistic ITR values,the ITR barely affects heat diffusion mechanical stresses of the model.Whereas,ITR may cause serious problem to the functionality and the efficiency of some electronic components.On the other hand,extremely large ITR leads to a decrease in the thermal stress in the diode.Good control on the ITR may help to improve the performance of high-power devices in the future,in addition to providing more efficient electrical contacts.

Physical simulations and experimental results of 4H-SiC MESFETs on high purity semi-insulating substrates

In this paper we report on DC and RF simulations and experimental results of 4H-SiC metal semiconductor field effect transistors （MESFETs） on high purity semi-insulating substrates. DC and small-signal measurements are compared with simulations. We design our device process to fabricate n-channel 4H-SiC MESFETs with 100 #m gate periphery. At 30 V drain voltage, the maximum current density is 440 mA/mm and the maximum transconductance is 33 mS/mm. For the continuous wave （CW） at a frequency of 2 GHz, the maximum output power density is measured to be 6.6 W/mm, with a gain of 12 dB and power-added efficiency of 33.7%. The cut-off frequency （fT） and the maximum frequency （fmax） are 9 GHz and 24.9 GHz respectively. The simulation results of fT and fmax are 11.4 GHz and 38.6 GHz respectively.

基于国产单晶衬底的150 mm 4H-SiC同质外延技术进展

高阻断电压、大功率密度、高转化效率是电力电子器件技术持续追求的目标,基于4H-SiC优异的材料特性,在电力电子器件应用方面具有广阔的发展前景。围绕SiC MOSFET器件对外延材料的需求,介绍了国内外主流的SiC外延设备及国产SiC衬底的发展,并重点介绍了宽禁带半导体电力电子器件国家重点实验室在国产150 mm(6英寸)SiC衬底上的高速外延技术进展。通过关键技术攻关,实现了150 mm SiC外延材料表面缺陷密度≤0.5 cm-2,BPD缺陷密度≤0.1 cm-2,片内掺杂浓度不均匀性≤5%,片内厚度不均匀性≤1%。基于自主外延材料,实现了650~1200 V SiC MOSFET产品商业化以及6.5~15 kV高压SiC MOSFET器件的产品定型。

具有异质结体二极管和N包围型P柱的4H-SiC超结MOSFET

利用TCAD仿真研究了一种具有异质结体二极管与N包围型P柱超结的4H-SiC UMOSFET(SJH-MOSFET)。通过在SJH-MOSFET中引入异质结和具有电荷平衡的超结结构,能够有效地优化器件的击穿电压、比导通电阻、反向恢复特性。研究结果表明,薄轻掺杂的电流扩展层(CSL)和N型包围使得耗尽区变窄,并为电流的流动提供了两个扩散路径,其中CSL使得电子快速地水平扩散,而N型包围允许电子可以垂直地流动,改进后结构的耐压提升了13.6%,栅槽底部高电场降低了10.5%,比导通电阻降低了10.5%,开启时间降低了38.4%,关断时间降低了44.7%;体区嵌入P+多晶硅与漂移区接触形成异质结体二极管,由于异质结特殊的能带结构,使得体二极管在导通时,P+多晶硅里空穴较少地流入到漂移区,使反向恢复电荷降低了42.96%,反向恢复时间降低了4.17%。

基于聚氨酯垫的4H-SiC单晶衬底研磨性质研究

4H-SiC单晶是典型的难加工材料,研磨加工后表面损伤的密度和深度直接影响后续抛光工序的质量和效率。采用普通铸铁盘研磨工艺会导致晶圆表面划痕多、边缘破片以及去除率不稳定等问题。本实验采用聚氨酯垫研磨工艺,减少研磨划痕,提高了研磨后的表面质量,实现了SiC衬底的精准研磨。通过改变金刚石磨料粒度、磨抛盘转速、研磨压强进行SiC衬底的研磨实验,探究最优工艺参数及各条件对研磨效果的影响规律。实验结果表明:随着研磨盘速度增大,研磨的去除率增大,其对应的粗糙度先降低后升高;增大金刚石磨料的粒径会增大研磨的去除率,但研磨后表面粗糙度也会持续增大;通过增加研磨压强,材料的去除率和表面粗糙度都将增加,但去除率增加的速率由快变慢,而粗糙度增加的速率逐渐加快。综合考虑,采用聚氨酯垫研磨时,较优研磨工艺参数为:金刚石研磨液浓度为3%,金刚石粒径为1μm,研磨液供给速度为5 mL/min,研磨压强为47 kPa,研磨转速35 r/min。该工艺下SiC材料的去除率为0.7μm/h,研磨后SiC衬底的表面粗糙度为24 nm。

4H-SiC SP-MPS二极管迅回效应的仿真研究

为了抑制4H-SiC MPS二极管的迅回效应,在传统结构的肖特基结下方引入P-轻掺杂区形成SP-MPS结构。给出简化电阻模型和等效电路图分析MPS二极管的正向导通特性,仿真了肖特基区宽度、P+区结深及P-区深度等关键参数对迅回效应的影响。研究结果表明,减小肖特基区宽度、增加P+区结深均可有效抑制迅回效应。SPMPS结构通过添加P-轻掺杂区来调整肖特基势垒高度进而控制转折电压的大小,增加P-区深度对迅回效应具有抑制作用,但与P-区掺杂浓度基本无关。对比传统MPS结构,在P-区深度为0.25μm、掺杂浓度为1×10^(17)cm^(-3)的条件下,SP-MPS结构的肖特基势垒高度增加了35.7%,转折电压降低了73.2%,明显改善迅回效应对MPS二极管正向特性的影响。

Impacts of hydrogen annealing on the carrier lifetimes in p-type 4H-SiC after thermal oxidation

Thermal oxidation and hydrogen annealing were applied on a 100μm thick Al-doped p-type 4H-Si C epitaxial wafer to modulate the minority carrier lifetime,which was investigated by microwave photoconductive decay(μ-PCD).The minority carrier lifetime decreased after each thermal oxidation.On the contrary,with the hydrogen annealing time increasing to3 hours,the minority carrier lifetime increased from 1.1μs(as-grown)to 3.14μs and then saturated after the annealing time reached 4 hours.The increase of surface roughness from 0.236 nm to 0.316 nm may also be one of the reasons for limiting the further improvement of the minority carrier lifetimes.Moreover,the whole wafer mappings of minority carrier lifetimes before and after hydrogen annealing were measured and discussed.The average minority carrier lifetime was up to 1.94μs and non-uniformity of carrier lifetime reached 38%after 4-hour hydrogen annealing.The increasing minority carrier lifetimes could be attributed to the double mechanisms of excess carbon atoms diffusion caused by selective etching of Si atoms and passivation of deep-level defects by hydrogen atoms.

Analysis of high-temperature performance of 4H-SiC avalanche photodiodes in both linear and Geiger modes

The high-temperature performance of 4H-SiC ultraviolet avalanche photodiodes(APDs)in both linear and Geiger modes is extensively investigated.During the temperature-dependent measurements,a fixed bias voltage is adopted for the device samples,which is much more practical and important for high-temperature applications.The results show that the fabricated 4H-SiC APDs are very stable and reliable at high temperatures.As the temperature increases from room temperature to 425 K,the dark current at 95%of the breakdown voltage increases slightly and remains lower than40 pA.In Geiger mode,our 4H-SiC APDs can be self-quenched in a passive-quenching circuit,which is expected for highspeed detection systems.Moreover,an interesting phenomenon is observed for the first time:the single-photon detection efficiency shows a non-monotonic variation as a function of temperature.The physical mechanism of the variation in hightemperature performance is further analyzed.The results in this work can provide a fundamental reference for researchers in the field of 4H-SiC APD ultraviolet detectors.

4H-SiC p-n结基于精确碰撞电离模型的雪崩倍增因子研究

雪崩倍增效应是4H-SiC雪崩光电二极管、功率半导体器件等器件的关键机理。作为其中最重要的物理参数,雪崩倍增因子(M)的精确解析表达式目前未见报道。文章提出4H-SiC p-n结M的精确计算方法及其解析表达式。基于更准确的碰撞电离模型,通过MATLAB对4H-SiC单边突变结(p^(+)-n)电子和空穴的碰撞电离积分(I)进行精确的数值计算,给出击穿电压(BV)随掺杂浓度的经验表达式,进一步提出电离积分随外加电压及掺杂浓度的拟合表达式。此外,对外加电压接近BV的情形进行细致的相对误差分析,表明电子电离积分受电场影响显著。对于雪崩光电二极管及功率器件较宽的BV范围,所提出的拟合表达式在外加反向偏压大于0.65BV时具有较高的精确度(相对误差小于5%)。