一种16位110 dB无杂散动态范围的低功耗SAR ADC

该文设计了一款16位、转换速率为625 kS/s的逐次逼近寄存器型模数转换器(SAR ADC)。改进的采样保持电路结构,优化了采样线性度和噪声性能。采用分段结构设计电容型数模转换器并使用混合方式的电容切换方案,减小面积和能耗。利用扰动注入技术提升ADC的线性度。比较器采用两级积分型预放大器减小噪声,利用输出失调存储技术及优化的电路设计减小了比较器失调电压和失调校准引入的噪声,优化并提升了比较器速度。芯片采用CMOS 0.18μm工艺设计和流片,ADC核心面积为1.15 mm^(2)。测试结果表明,在1 kHz正弦信号输入下,ADC差分输入峰峰值幅度达8.8 V,信纳比为85.9 dB,无杂散动态范围为110 dB,微分非线性为-0.27/+0.32 LSB,积分非线性为-0.58/+0.53 LSB,功耗为4.31 mW。

高精度低功耗噪声整形SAR ADC设计

针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。

一种具有1~128倍可变增益放大器的低功耗Sigma⁃Delta ADC

为满足传感器应用的低功耗需求,设计并实现了一种低功耗Sigma⁃Delta模数转换器(ADC)芯片。该ADC采用一阶全差分开关电容Sigma⁃Delta调制器,且集成了可编程增益放大器(PGA)和Bandgap;使用1.5 bit量化结构,相较于1 bit量化结构减小了3 dB的量化误差;使用优化的反馈电路,减小了电容失配引入的误差;PGA采用轨到轨的运放电路拓扑,增大了整个芯片的电压适应范围。基于180 nm CMOS工艺对该ADC进行了设计和流片。测试结果表明:该Sigma⁃Delta ADC在采样频率512 kHz、过采样率(OSR)为256时,峰值信噪谐波失真比(SNDR)和有效位数(ENOB)分别为75.29 dB和12.21 bit,芯片功耗仅为0.92 mW。芯片能在2.3~5.5 V宽电源电压范围内正常工作,可实现最大128 V/V的增益。适用于小型传感器的信号测量应用,可以满足小型传感器低功耗、高精度的需求。

A 128×128 SPAD LiDAR sensor with column-parallel 25 ps resolution TA-ADCs

This paper presents a design of single photon avalanche diode(SPAD)light detection and ranging(LiDAR)sensor with 128×128 pixels and 128 column-parallel time-to-analog-merged-analog-to-digital converts(TA-ADCs).Unlike the conventional TAC-based SPAD LiDAR sensor,in which the TAC and ADC are separately implemented,we propose to merge the TAC and ADC by sharing their capacitors,thus avoiding the analog readout noise of TAC’s output buffer,improving the conversion rate,and reducing chip area.The reverse start-stop logic is employed to reduce the power of the TA-ADC.Fabricated in a 180 nm CMOS process,our prototype sensor exhibits a timing resolution of 25 ps,a DNL of+0.30/−0.77 LSB,an INL of+1.41/−2.20 LSB,and a total power consumption of 190 mW.A flash LiDAR system based on this sensor demonstrates the function of 2D/3D imaging with 128×128 resolution,25 kHz inter-frame rate,and sub-centimeter ranging precision.

一种具有纹波消除技术的10 bit SAR ADC

逐次逼近寄存器模数转换器(SAR ADC)在逐次逼近的过程中,电容的切换会使参考电压上出现参考纹波噪声,该噪声会影响比较器的判定,进而输出错误的比较结果。针对该问题,基于CMOS 0.5μm工艺,设计了一种具有纹波消除技术的10 bit SAR ADC。通过增加纹波至比较器输入端的额外路径,将参考纹波满摆幅输入至比较器中;同时设计了消除数模转换器(DAC)模块,对参考纹波进行采样和输入,通过反转纹波噪声的极性,消除参考纹波对ADC输出的影响。该设计将信噪比(SNR)提高到56.75 dB,将有效位数(ENOB)提升到9.14 bit,将积分非线性(INL)从-1~5 LSB降低到-0.2~0.3 LSB,将微分非线性(DNL)从-3~4 LSB降低到-0.5~0.5 LSB。

低分辨率ADCs/DACs和低质量RF链技术辅助的D2D协助去蜂窝大规模MIMO系统

为了有效地解决当前频谱资源稀缺的问题,同时满足未来对大规模的无线接入和高速率的急剧需求,本文提出了低分辨率模数转换(analog-to-digital converters, ADCs)/数模转换(digital-to-analog converters, ADCs)和低质量射频(radio frequency, RF)链技术辅助的终端直连(device-to-device, D2D)协助去蜂窝大规模多入多出(multiple-input multiple-output, MIMO)系统,通过D2D分担数据传输压力,低分辨率ADCs/DACs和低质量RF链技术可用于减少硬件开销,从而提升系统传输速率与能量效率。研究发现增加接入点(access points, APs) APs数量、AP天线数量和D2D用户(D2D user, DUE)天线数量可以有效地提升系统的总速率,当比特数等于16或质量因子等于1时,系统总速率和总能量效率达到最优。此外,增加DUEs密度可以极大地提升系统的性能。研究结果为未来去蜂窝大规模MIMO的实际部署提供了参考方案。

高精度高摆幅多工位ADC测试系统设计

基于V93000 ATE设计了一种采用外加电源升压变换模块及可变增益仪器仪表运算放大器,以解决大输入摆幅高精度多工位ADC的量产测试需求的测试方案。理论分析和测试验证结果表明,该ADC测试系统可分别产生峰峰值超过29 V的Ramp波和正弦波测试信号,测试信号SNR优于105 dB、THD优于-103 dB,可以满足16 bit、±10 V甚至以上高输入摆幅多工位ADC的大批量量产测试需求。

一种高速A/D转换器时域重构技术研究

A/D转换器在航空航天系统中的重要元器件,随着器件转换时钟频率不断提高而其工作环境不断恶化,如何准确测试其时间参数对于全面评价A/D转换器性能特别重要。目前对于高速A/D转换器时间参数测试,主流方法是通过示波器直接测试其输出,该方法对于示波器采样速度要求比较高。文章提出一种高速A/D转换器时域重构技术,可以通过计算机数字信号处理方法来实现高速A/D转换器时间参数测试,同时避免对示波器采样速度的依赖。同时,在研究高速A/D转换器时域重构技术方法及其应用的基础上,通过了相关试验验证。

大带宽采样下通用接收机ADC设计

为了解决宽带采样通用接收机中模数转换器(ADC)的抗干扰问题,定量分析采样带宽内存在不同功率的其他信号时对有用信号量化时造成的ADC输出信噪比的损失,对ADC输出信噪比的损失与输入有用信号信噪比、中频预选滤波器带宽内信号的信干噪比、输入信号功率、有用信号带宽、ADC采样带宽、ADC量化位数的关系进行理论分析与推导,并进行多场景下的仿真验证。结果表明,研究中对ADC输入和量化噪声的理论分析及推导是正确的,对于卫星通信中带宽20 kHz的典型信号,当要求输出信噪比损失小于0.1 dB时,要实现20,30和40 dB的抗干扰能力所需要的最小量化位数分别为8位,9位和10位。宽带采样下接收机ADC的设计,可获得最佳的性价比,并利于在工程中控制成本,对于宽窄带兼容接收有一定的工程意义。

高精度SAR ADC电容阵列设计及校准算法

在高精度逐次逼近寄存器模数转换器(SAR ADC)中,电容阵列是SAR ADC的核心之一。电容阵列中的电容失配问题是导致转换精度降低的一个重要原因。为了尽可能改善这一问题,设计了一种6+6+6分段电容阵列,并且基于这种阵列设计了权重迭代算法的前台数字校准。该方法不需要额外的电容阵列,利用自身的电容阵列与比较器量化出电容失配,计算出每一位输出码的权重校准系数,用来对正常量化出的输出码进行编码,实现校准功能。仿真结果表明,引入电容失配的18 bit SAR ADC经过该算法校准后,信噪比(SNR)从77.6 dB提升到107.6 dB,无杂散动态范围(SFDR)从89.8 dB提升到125.6 dB,有效位数(ENOB)从12.54 bit提升到17.54 bit。在SMIC 0.18μm工艺下,该校准算法对高精度SAR ADC的动态性能具有较大提升。

一款7 Bit 250 Msps射频采样SAR ADC的设计

针对软件无线电架构的导航接收机对模数转换器的高输入带宽、高速及低功耗的需求,通过集成低功耗宽带采样保持电路及新型非二进制权重的电容阵列数模转换器电路,采用逐次逼近型模数转换器架构,设计实现了一款射频直接采样SAR模数转换器。采用55 nm CMOS工艺电路设计、版图设计、仿真及硅流片验证,测试结果表明,该ADC实现了34 dB SNDR、36 dB SFDR和1.6 GHz的模拟输入信号带宽。该ADC的版图面积为670μm×390μm,功耗为9.6 mW。

工艺-电压-温度综合稳健的亚1 V 10位SAR ADC

采用0.11-μm CMOS工艺设计了一款10位亚1 V工艺-电压-温度(Process-Voltage-Temperature,PVT)综合稳健的逐次逼近寄存器型(Successive-Approximation-Register,SAR)模数转换器(Analog-to-Digital Converter,ADC)IP核.由于SAR ADC数字化程度较高,为了降低整体功耗,采用小于标准电压的亚1 V供电.然而,对于异步SAR ADC,在低压下面临严峻的PVT不稳健问题,传统采用固定延迟电路的方式无法应对所有的PVT偏差,会导致ADC良率下降.提出一种用于异步SAR ADC的可配置延迟调控技术,采用3输入译码器调节延迟电路的电流,以满足ADC在多种PVT组合下所需的延时,在TT,SS,FF,SF,FS这5种工艺角,0.9~1 V供电范围和-40~85℃的温度范围下,均取得了良好的动态特性.在0.95 V供电,采样速率为200 kS/s时,总功耗为2.24μW,FoM值仅为16.46 fJ/Conv.-step.

Numeric Simulation of Single Passage Ternary Turbulence Model in Hydraulic Torque Converter

Based on the renormalization group theory, a hydraulic torque converter 3 D turbulent single flow passage model is constructed and boundary condition is determined for analyzing the influence of the fluid field characteristic and parameters on the macroscopic model. Numerical simulation of the single fluid path is processed by computational fluid dynamics and the calculated results approach to experimental data well, and especially in low transmission ratio the torque and head results are more close to experimental data than the calculated results of beam theory. This shows that the appropriate ternary analysis method and reasonable assumption of boundary condition may analyze the flow field more precisely and predict the performance of torque converter more accurately.

Numerical simulation of the flow field of a flat torque converter

A flexible flat torque converter was proposed to fulfill the requirement of miniaturization and power density maximization for automobiles.Constructed by two arcs joined by lines,the torus was designed directly from design path.The influence of flatness on the performance of the torque converter was evaluated.The software CFX and standard k-ε model were adopted to simulate the internal flow fields of the torque converter under different flatness ratios.The results indicated that the performance of the torque converter got worse as the flatness declined,but the capacity of pump increased.The efficiency and the torque ratio dropped slightly as the flatness ratio decreased.So the torque converter could be squashed appropriately to get high power density without too much efficiency sacrifice.But when the flatness ratio was below 0.2,there was a significant drop in the efficiency.

基于数字自校准的14位SAR ADC的设计

为了降低电容型模数转换器(ADC)中的电容失配带来的非线性影响,提出了一种基于复用低位电容自校准的逐次逼近型(SAR)ADC电路结构,利用低位电容转化高位电容失配引起的误差电压,实现高位电容失配校准。在55 nm CMOS工艺下实现了该ADC结构。该结构ADC工作过程为失调误差提取与正常转换两阶段,失调误差提取阶段中利用低位电容将高位电容失配产生的误差电压转换为误差码并存储,将误差码与正常转化数字码求和得到最终的数字输出,实现电容失配自校准。为了提高ADC采样速率,该结构通过分段结构将电容阵列分为三段降低了单位电容数量。仿真结果表明,在1.2 V电源电压,80 MSPS采样速率下,引入电容失配后电路功耗为3.72 mW,有效位数为13.45 bit,信噪失真比(SNDR)为82.75 dB,相比未校准分别提高4.41 bit,26.58 dB。

血清GSDMD、ACE2在小儿川崎病中的表达水平及临床意义研究

目的 探索血清焦孔素蛋白D(GSDMD)、血管紧张素转化酶2(ACE2)在小儿川崎病(KD)患儿中的表达水平及临床意义。方法 收集2020年1月至2022年1月该院诊治的90例KD患儿为KD组,根据KD患儿是否发生冠状动脉损伤(CAL),将KD组分为CAL组(32例)和非CAL组(58例),选取同期因急性呼吸道感染发热住该院的患儿50例为发热对照组,另选取同期该院儿外科行择期手术的腹股沟斜疝患儿50例为对照组。采用酶联免疫吸附试验检测血清GSDMD、ACE2水平。Pearson相关分析血清GSDMD、ACE2与临床指标的相关性。多因素Logisitic回归分析KD患者发生CAL的影响因素。受试者工作特征(ROC)曲线分析血清GSDMD、ACE2对KD患儿发生CAL的诊断价值。结果 KD组血清GSDMD、ACE2水平高于发热对照组和对照组,差异有统计学意义(均P<0.05)。相比于非CAL组,CAL组KD患儿发热持续时间、丙种球蛋白治疗时间、红细胞沉降率、血小板计数、C反应蛋白、GSDMD、ACE2水平均明显较高,而血钠、白蛋白明显较低,差异有统计学意义(均P<0.05)。Pearson相关分析结果,KD组患儿血清GSDMD、ACE2水平与发热持续时间、丙种球蛋白治疗时间、红细胞沉降率、血小板计数、C反应蛋白呈正相关(均P<0.05),与血钠、白蛋白呈负相关(均P<0.05)。多因素Logistic回归分析结果显示,血清GSDMD、ACE2升高是影响KD患儿发生CAL的独立危险因素。ROC曲线分析结果显示,血清GSDMD、ACE2两项联合检测KD患儿发生CAL的曲线下面积(AUC)及其95%CI为0.918(0.868~0.949),明显大于血清GSDMD、ACE2单项检测的AUC及其95%CI[依次为0.838(0.789~0.887)、0.865(0.811~0.912)],差异有统计学意义(Z=5.116、4.217,均P<0.05)。结论 血清GSDMD、ACE2两项联合检测对于KD患儿发生CAL具有较高的诊断价值。

A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

Performance Optimization of Torque Converters Based on Modified 1D Flow Model

A methodology for performance optimization of torque converters is put forward based on the one-dimensional (1D) flow model. It is found that the inaccuracy of 1D flow model for predicting hydraulic performance at the low speed ratio is mainly caused by the separation phenomenon at the stator cascade which is induced by large flow impinging at the pressure side of the stator blades. A semi-empirical separation model is presented and incorporated to the original 1D flow model. It is illustrated that the improved model is able to predict the circumferential velocity components accurately, which can be applied to performance optimization. Then, the Pareto front is obtained by using the genetic algorithm (GA) in order to inspect the coupled relationship among stalling impeller torque capacity, stalling torque ratio and efficiency. The efficiency is maximized on the premise that a target stalling impeller torque capacity and torque ratio are achieved. Finally, the optimized result is verified by the computational fluid dynamics(CFD) simulation, which indicates that the maximal efficiency is increased by 0.96%.

Analytical Modelling and Experiment of Novel Rotary Electro-Mechanical Converter with Negative Feedback Mechanism for 2D Valve

The manufacturing of spiral groove structure of two-dimensional valve(2D valve)feedback mechanism has shortcomings of both high cost and time-consuming.This paper presents a novel configuration of rotary electro-mechanical converter with negative feedback mechanism(REMC-NFM)in order to replace the feedback mechanism of spiral groove and thus reduce cost of valve manufacturing.In order to rapidly and quantitative evaluate the driving and feedback performance of the REMC-NFM,an analytical model taking leakage flux,edge effect and permeability nonlinearity into account is formulated based on the equivalent magnetic circuit approach.Then the model is properly simplified in order to obtain the optimal pitch angle.FEM simulation is used to study the influence of crucial parameters on the performance of REMC-NFM.A prototype of REMC-NFM is designed and machined,and an exclusive experimental platform is built.The torque-angle characteristics,torque-displacement characteristics,and magnetic flux density in the working air gap with different excitation currents are measured.The experimental results are in good agreement with the analytical and FEM simulated results,which verifies the correctness of the analytical model.For torque-angle characteristics,the overall torque increases with both current and rotation angle,which reaches about 0.48 N·m with 1.5 A and 1.5°.While for torque-displacement characteristics,the overall torque increases with current yet decrease with armature displacement due to the negative feedback mechanism,which is about 0.16 N·m with 1.5 A and 0.8 mm.Besides,experimental results of conventional torque motor are compared with counterparts of REMC-NFM in order to validate the simplified model.The research indicates that the REMC-NFM can be potentially used as the electro-mechanical converter for 2D valves in civil servo areas.

基于先进CMOS工艺的多通道Gbps LVDS接收器

在SIP(System In a Package)系统中集成具有LVDS(Low-Voltage Differential Signal)接口的多通道高速模数转换器(Analog-to-Digital Converter,ADC)时,面临不同LVDS输出通道延时不同所导致的数据采集错误的问题,为此设计了一个多通道自适应LVDS接收器。通过采用数据时钟恢复技术产生一个多相位的采样时钟,并结合ADC的测试模式来确认每一个通道的采样相位,能够自动对每一个通道的延时分别进行调整,以达到对齐各通道采样相位点,保证数据正确采集的目的。最后,基于先进CMOS工艺进行了接收器的设计、仿真、后端设计实现和流片测试,仿真和流片后的板级测试结果均表明该接收器能够对通道延迟进行自动调节以对齐采样相位,且最大的采样相位调节范围为±3 bit,信噪比大于65 dB,满足了设计要求和应用需求。