Novel Optical Analog-To-Digital Converter Based on Optical Time Division Multiplexing

A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.

Sampling and Reconstruction of Zero-Order Hold Signals by Parallel RC Filters

In this work we describe a reconstruction algorithm for zero-order hold (ZOH) waveforms measured by a parallel sam-pling scheme. In the method the ZOH signal is fed to a parallel network consisting of resistor-capacitor (RC) filters, whose outputs are sampled simultaneously. The algorithm reconstructs N previous samples of the input signal from output samples of N parallel RC circuits. The method is especially useful in sampling and reconstruction of the ZOH signals produced by the digital-to-analog converters. Using the parallel sampling method the sampling rate of the analog-to-digital converters can be increased by a factor of N. We discuss a variety of applications such as reconstruction of ZOH pulse sequences produced by ultra wide band (UWB) transmitters.

一种基于冗余位结构CDAC的12 bit SAR ADC

提出一种基于非二进制冗余位结构CDAC的12 bit全差分逐次逼近型模拟数字转换器(SAR ADC)。传统SAR ADC中CDAC的单位电容数量随位数指数增长,且采用全差分结构的电容数量是单端结构的两倍,导致CDAC建立时间过长。为此,设计一种加入冗余位的分段式电容阵列,减少单位电容数量,提高CDAC建立速度。动态比较器的比较速度快,会导致数字码误判,通过加入冗余位弥补比较器对数字码误判的缺陷;采用底板采样技术,避免沟道电荷注入和时钟馈通,提高采样精度;采用SMIC 130 nm CMOS工艺。在电源电压1.2 V、20 MS/s采样率下,对1024点FFT仿真。结果显示:当输入频率(9.824 MHz)接近奈奎斯特频率时,该ADC的整体信噪失真比(SNDR)达到72.42 dB,有效位数(ENOB)达到11.73 bit;无杂散动态范围(SFDR)达到88.4 dBc,功耗为1.29 mW。

一种16位110 dB无杂散动态范围的低功耗SAR ADC

该文设计了一款16位、转换速率为625 kS/s的逐次逼近寄存器型模数转换器(SAR ADC)。改进的采样保持电路结构,优化了采样线性度和噪声性能。采用分段结构设计电容型数模转换器并使用混合方式的电容切换方案,减小面积和能耗。利用扰动注入技术提升ADC的线性度。比较器采用两级积分型预放大器减小噪声,利用输出失调存储技术及优化的电路设计减小了比较器失调电压和失调校准引入的噪声,优化并提升了比较器速度。芯片采用CMOS 0.18μm工艺设计和流片,ADC核心面积为1.15 mm^(2)。测试结果表明,在1 kHz正弦信号输入下,ADC差分输入峰峰值幅度达8.8 V,信纳比为85.9 dB,无杂散动态范围为110 dB,微分非线性为-0.27/+0.32 LSB,积分非线性为-0.58/+0.53 LSB,功耗为4.31 mW。

针对高转速A/D采集的自适应平滑处理方法

船舶领域常用瞬间转速测量对各类大型机械设备进行运行状态监测及信号控制,为了提高瞬时转速测量的精度,从而提高船舶设备运行控制的准确性以及设备健康状态评估的有效性,基于传统模数转换(A/D)采集的采集转速方法——测频率法和测周期法,通过对A/D转速测量点数进行多周期平滑处理,并加入转速分段测量的自适应机制,提高A/D采集瞬时高转速的精度。在进行模拟仿真与理论结果比较验证后,进一步开展在实际测量中自适应平滑处理方法对转速测量精度影响的研究。仿真及试验结果表明,采用的转速测量方法针对不同的转频均可有效降低转速测量误差,研究成果可为船舶机械设备转速测量提供一定参考。

应用于5.8 GHz雷达中的12 bit SAR ADC

为满足5.8 GHz雷达系统的需要,在HLMC55LP工艺中设计了一款12 bit SAR ADC,ADC的采样率为500 kHz/250 kHz两档可调,采用单调电容开关时序,且在电容阵列的高位部分加上2个冗余位设计,该冗余位对高位的CDAC建立误差,比较器误差都有一定的容忍能力,可以带来ADC性能上的提升。系统采用上极板采样,可以在采样周期结束的瞬间就开始逐位比较过程,省去了采用底极板采样第一拍CDAC建立的过程,提高了转换速度,相对于底极板采样也节省了一定的开关功耗。后仿结果表明,模拟输入20 kHz差分中频信号,在500 kHz采样频率,3.3 V电源电压下,ADC的有效位数为11.56 bit,SNR为71.04 dB,SFDR为80.37 dBc,功耗约为2 mW。

Comparison of sampling designs for calibrating digital soil maps at multiple depths

Digital soil mapping (DSM) aims to produce detailed maps of soil properties or soil classes to improve agricultural management and soil quality assessment. Optimized sampling design can reduce the substantial costs and efforts associated with sampling, profile description, and laboratory analysis. The purpose of this study was to compare common sampling designs for DSM, including grid sampling (GS), grid random sampling (GRS), stratified random sampling (StRS), and conditioned Latin hypercube sampling (cLHS). In an agricultural field (11 ha) in Quebec, Canada, a total of unique 118 locations were selected using each of the four sampling designs (45 locations each), and additional 30 sample locations were selected as an independent testing dataset (evaluation dataset). Soil visible near-infrared (Vis-NIR) spectra were collected in situ at the 148 locations (1 m depth), and soil cores were collected from a subset of 32 locations and subdivided at 10-cm depth intervals, totaling 251 samples. The Cubist model was used to elucidate the relationship between Vis-NIR spectra and soil properties (soil organic matter (SOM) and clay), which was then used to predict the soil properties at all 148 sample locations. Digital maps of soil properties at multiple depths for the entire field (148 sample locations) were prepared using a quantile random forest model to obtain complete model maps (CM-maps). Soil properties were also mapped using the samples from each of the 45 locations for each sampling design to obtain sampling design maps (SD-maps). The SD-maps were evaluated using the independent testing dataset (30 sample locations), and the spatial distribution and model uncertainty of each SD-map were compared with those of the corresponding CM-map. The spatial and feature space coverage were compared across the four sampling designs. The results showed that GS resulted in the most even spatial coverage, cLHS resulted in the best coverage of the feature space, and GS and cLHS resulted in similar prediction accuracies and spatial distributions of soil properties. The SOM content was underestimated using GRS, with large errors at 0–50 cm depth, due to some values not being captured by this sampling design, whereas larger errors for the deeper soil layers were produced using StRS. Predictions of SOM and clay contents had higher accuracy for topsoil (0–30 cm) than for deep subsoil (60–100 cm). It was concluded that the soil sampling designs with either good spatial coverage or feature space coverage can provide good accuracy in 3D DSM, but their performances may be different for different soil properties.

Sampling Designs for Validating Digital Soil Maps: A Review

Sampling design(SD) plays a crucial role in providing reliable input for digital soil mapping(DSM) and increasing its efficiency.Sampling design, with a predetermined sample size and consideration of budget and spatial variability, is a selection procedure for identifying a set of sample locations spread over a geographical space or with a good feature space coverage. A good feature space coverage ensures accurate estimation of regression parameters, while spatial coverage contributes to effective spatial interpolation.First, we review several statistical and geometric SDs that mainly optimize the sampling pattern in a geographical space and illustrate the strengths and weaknesses of these SDs by considering spatial coverage, simplicity, accuracy, and efficiency. Furthermore, Latin hypercube sampling, which obtains a full representation of multivariate distribution in geographical space, is described in detail for its development, improvement, and application. In addition, we discuss the fuzzy k-means sampling, response surface sampling, and Kennard-Stone sampling, which optimize sampling patterns in a feature space. We then discuss some practical applications that are mainly addressed by the conditioned Latin hypercube sampling with the flexibility and feasibility of adding multiple optimization criteria. We also discuss different methods of validation, an important stage of DSM, and conclude that an independent dataset selected from the probability sampling is superior for its free model assumptions. For future work, we recommend: 1) exploring SDs with both good spatial coverage and feature space coverage; 2) uncovering the real impacts of an SD on the integral DSM procedure;and 3) testing the feasibility and contribution of SDs in three-dimensional(3 D) DSM with variability for multiple layers.

Synthetic aperture radar tomography sampling criteria and three-dimensional range migration algorithm with elevation digital spotlighting

Based on the general geometric model of multi-baseline Synthetic Aperture Radar Tomography （TomoSAR）, the three-dimensional （3-D） sampling criteria, the analytic expression of the 3-D Point Spread Function （PSF） and the 3-D resolution are derived in the 3-D wavenumber domain in this paper. Considering the relationship between the observation geometry and the size of illuminated scenario, a 3-D Range Migration Algorithm with Elevation Digital Spotlighting （RMA-EDS） is proposed. With this algorithm 3-D images of the area of interest can be directly and accurately reconstructed in the 3-D space avoiding the complex operations of 3-D geometric correction. Finally, theoretical analyses and simulation results are presented to demonstrate the shift-varying property of the 3-D PSF and the spatialvarying property of the 3-D resolution and to demonstrate the validity of the 3-D RMA-EDS.

基于DSP和FPGA的数字示波器设计

为了测量激光发生器电源模块的重要参数,提出了一种基于DSP和FPGA的数字示波器。分别分析了实时采样和等效采样的基本原理、基于DESO滤波器的滤波原理及其数学表达式;在此基础上,给出了幅度类参数和周期类参数的计算方法,并对各类指标进行了详细计算。整个数字示波器嵌入在激光发生器整体系统中,工程应用性强、集成度高。测试结果表明,数字示波器运行稳定可靠,能够满足设计要求,具有很高的应用价值。

基于平均频谱测试高速ADC动态参数的方法

利用快速傅里叶变换进行模数转换器(ADC)动态参数测试很难做到相干采样和整周期截断,因此非相干采样存在必然性,由此造成的频谱泄漏将影响动态参数的测量结果。针对此问题,提出了一种基于平均频谱测试高速ADC动态参数的方法。基于MATLAB构建了验证平台,采用美国模拟器件公司(ADI)的典型高速ADC产品的行为级动态模型进行了仿真验证。仿真结果表明,在非相干程度最大的情况下,基于不同窗函数的平均频谱测试得到的动态参数误差低于1.67%,且达到了IEEE Std 1241-2000的测试标准,降低了测试系统构建难度和成本。

一种基于DSP和采样ADC的数字锁定放大器

探讨了用 DSP(数字信号处理器 )和采样 ADC(模数转换器 )实现数字锁定放大器的一种方法。在整数个周期内对被测信号进行采样得到信号序列 ,由数学运算得到参考序列 ,通过计算信号序列和参考序列的互相关函数就可实现数字相敏检测。文中还对数字相敏检测的频率特性进行了分析。最后 ,给出了实际设计的数字锁定放大器 ,它的工作频率范围是 10 Hz～ 30 k Hz,实验结果表明 ,可以用它来测量低信噪比的信号。

高分辨率流水线A/D转换器采样电容优化研究

讨论了流水线A/D转换器的工作原理,定量分析了开关电容增益块中最重要的两个热噪声源:采样开关和放大器的热噪声。以此为基础,提出了使功耗最小化的采样电容选择方法,以及在简单模型下的取值。在对A/D转换器进行功耗优化时,分析结果对选择采样电容和每级分辨率具有指导意义。

用于带数字校正12位40 MS/s流水线ADC的MDAC电路及数模接口

设计了一个用于40 MHz采样率,12位精度流水线A/D转换器第一级的MDAC电路。该电路采用高增益带宽积的增益自举放大器,在3.5pF负载电容下,可以在8ns内稳定在最终值的0.01%;设计了低失调、低回踢噪声比较器。蒙特卡罗分析表明,失调电压小于7mV。电路采用SMIC0.35μm/3.3V CMOS工艺,用于一个带数字校正的流水线A/D转换器。在MDAC中加入一个D/A接口电路,可以在不引入过多模拟电路的前提下,配合数字校正部分完成其校正功能。

利用过采样技术提高ADC测量分辨率

针对目前单片机内嵌ADC分辨率较低,而外接高分辨率ADC成本又较高的情况,提出了用“过采样”技术使在有用的测量频带内的信噪比得到改善,从而提高ADC测量的分辨率。并利用Matlab对其结论进行仿真,且在TMS320LF2407 DSP上予以实现,结果表明信噪比和测量分辨率明显提高。

基于FPGA的高速串行AD转换器控制设计与实验研究

在对靶场光电仪器进行外场数据分析时,需要对仪器接收到的多种数据信号进行采集,为提高采集过程中数字控制系统A/D转换效率,并简化数据采集系统硬件,设计了基于FPGA控制AD7890芯片A/D转换和转换数据串行输出方案。介绍了串行多通道A/D转换器AD7890的工作原理,给出了在Xilinx公司的ISE 10.1软件开发平台下程序设计和仿真图,并进行了基于FPGA器件Virtex-4处理器硬件开发平台下的实验。实验表明,FPGA的控制是成功的,AD7890输出的二进制值010000000000和001001100111与加入到输入端的模拟电压5V和3V完全一致,充分发挥了12位AD7890的高精度特点。

高速ADC频域特性测试系统的设计

针对传统专用高速模数转换器频域特性测试系统构建难度大、成本高的问题,利用基于加窗和插值FFT算法的测试方法,提出一种低成本高速ADC频域特性测试系统,给出ADC采样时钟驱动电路、ADC输入信号驱动电路、FIFO缓存电路及USB接口电路的关键设计技术。

QPSK调制的WCDMA信号的一种数模混合型解扩方法

从降低解扩电路功耗和提高运算速度两方面考虑,针对采用QPSK调制的宽带码分多址(WCDMA)信号,提出了一种数模混合型解扩方法。该方法采用二阶采样保持技术对QPSK信号进行时域离散化和正交分解,通过数字控制的模拟匹配滤波器组在模拟域进行相关运算。给出了二阶采样参数的选取原则和模拟匹配滤波器组的实现结构,通过仿真实验验证了该方法的有效性。与全数字的解扩方法相比,该方法无需高速A/D转换器和正交解调器。

一种CMOS视频D/A转换器的设计与应用

提出了一种10位200 MHz CMOS电流舵视频D/A转换器(DAC)实现电路。权衡线性度、功耗、面积以及弱化毛刺等因素,该DAC的高6位采用单位译码矩阵,低4位采用二进制加权阵列。采用新型开关策略,进一步提高单位译码矩阵的线性度;设计带平滑电路的电流源与差分开关电路,以提高动态性能。整个芯片采用新加坡特许半导体公司3.3 V工作电压、0.35μm2P2M CMOS工艺制造。DAC的面积为1.26 mm×0.78 mm,其积分非线性误差和微分非线性误差均小于±0.2 LSB。