The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization...The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.展开更多
This paper first presents an impossible differential property for 5-round Advanced Encryption Standard （AES） with high probability. Based on the property and the impossible differential cryptanalytic method for the ...This paper first presents an impossible differential property for 5-round Advanced Encryption Standard （AES） with high probability. Based on the property and the impossible differential cryptanalytic method for the 5-round AES, a new method is proposed for cryptanalyzing the 8-round AES-192 and AES-256. This attack on the reduced 8-round AES-192 demands 2^121 words of memory, and performs 2^148 8-round AES-192 encryptions. This attack on the reduced 8-round AES-256 demands 2^153 words of memory, and performs 2^180 8-round AES-256 encryptions. Furthermore, both AES-192 and AES-256 require about 2^98 chosen plaintexts for this attack, and have the same probability that is only 2^-3 to fail to recover the secret key.展开更多
The substitution table (S-Box) of Advanced Encryption Standard (AES) and its properties are key elements in cryptanalysis ciphering. We aim here to propose a straightforward method for the non-linear transformation of...The substitution table (S-Box) of Advanced Encryption Standard (AES) and its properties are key elements in cryptanalysis ciphering. We aim here to propose a straightforward method for the non-linear transformation of AES S-Box construction. The method reduces the steps needed to compute the multiplicative inverse, and computes the matrices multiplication used in this transformation, without a need to use the characteristic matrix, and the result is a modern method constructing the S-Box.展开更多
Image authentication techniques have recently received a lot of attention for protecting images against unauthorized access.Due to the wide use of the Internet nowadays,the need to ensure data integrity and authentica...Image authentication techniques have recently received a lot of attention for protecting images against unauthorized access.Due to the wide use of the Internet nowadays,the need to ensure data integrity and authentication increases.Many techniques,such as watermarking and encryption,are used for securing images transmitted via the Internet.The majority of watermarking systems are PC-based,but they are not very portable.Hardwarebased watermarking methods need to be developed to accommodate real-time applications and provide portability.This paper presents hybrid data security techniques using a zero watermarking method to provide copyright protection for the transmitted color images using multi-channel orthogonal Legendre Fourier moments of fractional orders(MFrLFMs)and the advanced encryption standard(AES)algorithm on a low-cost Raspberry Pi.In order to increase embedding robustness,the watermark picture is scrambled using the Arnold method.Zero watermarking is implemented on the Raspberry Pi to produce a real-time ownership verification key.Before sending the ownership verification key and the original image to the monitoring station,we can encrypt the transmitted data with AES for additional security and hide any viewable information.The receiver next verifies the received image’s integrity to confirm its authenticity and that it has not been tampered with.We assessed the suggested algorithm’s resistance to many attacks.The suggested algorithm provides a reasonable degree of robustness while still being perceptible.The proposed method provides improved bit error rate(BER)and normalized correlation(NC)values compared to previous zero watermarking approaches.AES performance analysis is performed to demonstrate its effectiveness.Using a 256×256 image size,it takes only 2 s to apply the zero-watermark algorithm on the Raspberry Pi.展开更多
Reconfigurable computing has grown to become an important and large field of research, it offers advantages over traditional hardware and software implementations of computational algorithms. The Advanced Encryption S...Reconfigurable computing has grown to become an important and large field of research, it offers advantages over traditional hardware and software implementations of computational algorithms. The Advanced Encryption Standard （AES） algorithm is widely applied in government department and commerce. This paper analyzed the AES algorithms with different cipher keys, adopted a novel key scheduler that generated the round key real-time, proposed a dynamically reconfigurable encryption system which supported the AES algorithm with different cipher keys, and designed the architecture of the reconfigurable system. The dynamically reconfigurable AES system had been realized on FPGA. The result proves that the reconfigurable AES system is flexible, lower cost and high security level.展开更多
This paper describes a high security data transmission system over X-band microwave frequency. The paper has two parts. The first part deals with encryption of binary data by Advanced Encryption Standard (AES) using V...This paper describes a high security data transmission system over X-band microwave frequency. The paper has two parts. The first part deals with encryption of binary data by Advanced Encryption Standard (AES) using VHDL modeling of Field Programmable Gate Array (FPGA). The second part deals with a novel idea of transmitting the encrypted data by using a single klystron. This requires the simultaneous generation of a pair of two independent RF frequencies from a reflex klystron working for X-band frequency range. In this scheme, the klystron is suitably biased on the repeller terminal and superimposed on a train of AES encrypted binary data so as to create two RF frequencies one corresponding to negative peaks and the other one to the positive peaks of the data resulting in an Frequency Shift Keying (FSK) signal. The results have been verified experimentally.展开更多
In order to improve the data throughput of the advanced encryption standard （AES） IP core while reducing the hardware resource consumption and finally achieving a tradeoff between speed and area, a mixed pipeline ar...In order to improve the data throughput of the advanced encryption standard （AES） IP core while reducing the hardware resource consumption and finally achieving a tradeoff between speed and area, a mixed pipeline architecture and reconfigurable technology for the design and implementation of the AES IP core is proposed. The encryption and decryption processes of the AES algorithm are achieved in the same process within the mixed pipeline structure. According to the finite field characterizations, the Sbox in the AES algorithm is optimized. ShiftRow and MixColumn, which are the main components in AES round transformation, are optimized with the reconfigurable technology. The design is implemented on the Xilinx Virtex2p xc2vp20-7 field programmable gate array （FPGA） device. It can achieve a data throughput above 2.58 Gbit/s, and it only requires 3 233 slices. Compared with other related designs of AES IP cores on the same device, the proposed design can achieve a tradeoff between speed and area, and obtain satisfactory results in both data throughput and hardware resource consumption.展开更多
文摘The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.
基金Supported by the Foundation of National Labora-tory for Modern Communications (51436030105DZ0105)
文摘This paper first presents an impossible differential property for 5-round Advanced Encryption Standard （AES） with high probability. Based on the property and the impossible differential cryptanalytic method for the 5-round AES, a new method is proposed for cryptanalyzing the 8-round AES-192 and AES-256. This attack on the reduced 8-round AES-192 demands 2^121 words of memory, and performs 2^148 8-round AES-192 encryptions. This attack on the reduced 8-round AES-256 demands 2^153 words of memory, and performs 2^180 8-round AES-256 encryptions. Furthermore, both AES-192 and AES-256 require about 2^98 chosen plaintexts for this attack, and have the same probability that is only 2^-3 to fail to recover the secret key.
文摘The substitution table (S-Box) of Advanced Encryption Standard (AES) and its properties are key elements in cryptanalysis ciphering. We aim here to propose a straightforward method for the non-linear transformation of AES S-Box construction. The method reduces the steps needed to compute the multiplicative inverse, and computes the matrices multiplication used in this transformation, without a need to use the characteristic matrix, and the result is a modern method constructing the S-Box.
基金funded by Princess Nourah bint Abdulrahman University Researchers Supporting Project Number (PNURSP2023R442)。
文摘Image authentication techniques have recently received a lot of attention for protecting images against unauthorized access.Due to the wide use of the Internet nowadays,the need to ensure data integrity and authentication increases.Many techniques,such as watermarking and encryption,are used for securing images transmitted via the Internet.The majority of watermarking systems are PC-based,but they are not very portable.Hardwarebased watermarking methods need to be developed to accommodate real-time applications and provide portability.This paper presents hybrid data security techniques using a zero watermarking method to provide copyright protection for the transmitted color images using multi-channel orthogonal Legendre Fourier moments of fractional orders(MFrLFMs)and the advanced encryption standard(AES)algorithm on a low-cost Raspberry Pi.In order to increase embedding robustness,the watermark picture is scrambled using the Arnold method.Zero watermarking is implemented on the Raspberry Pi to produce a real-time ownership verification key.Before sending the ownership verification key and the original image to the monitoring station,we can encrypt the transmitted data with AES for additional security and hide any viewable information.The receiver next verifies the received image’s integrity to confirm its authenticity and that it has not been tampered with.We assessed the suggested algorithm’s resistance to many attacks.The suggested algorithm provides a reasonable degree of robustness while still being perceptible.The proposed method provides improved bit error rate(BER)and normalized correlation(NC)values compared to previous zero watermarking approaches.AES performance analysis is performed to demonstrate its effectiveness.Using a 256×256 image size,it takes only 2 s to apply the zero-watermark algorithm on the Raspberry Pi.
基金Supported by the National Natural Science Foun-dation of China (60374008)
文摘Reconfigurable computing has grown to become an important and large field of research, it offers advantages over traditional hardware and software implementations of computational algorithms. The Advanced Encryption Standard （AES） algorithm is widely applied in government department and commerce. This paper analyzed the AES algorithms with different cipher keys, adopted a novel key scheduler that generated the round key real-time, proposed a dynamically reconfigurable encryption system which supported the AES algorithm with different cipher keys, and designed the architecture of the reconfigurable system. The dynamically reconfigurable AES system had been realized on FPGA. The result proves that the reconfigurable AES system is flexible, lower cost and high security level.
文摘This paper describes a high security data transmission system over X-band microwave frequency. The paper has two parts. The first part deals with encryption of binary data by Advanced Encryption Standard (AES) using VHDL modeling of Field Programmable Gate Array (FPGA). The second part deals with a novel idea of transmitting the encrypted data by using a single klystron. This requires the simultaneous generation of a pair of two independent RF frequencies from a reflex klystron working for X-band frequency range. In this scheme, the klystron is suitably biased on the repeller terminal and superimposed on a train of AES encrypted binary data so as to create two RF frequencies one corresponding to negative peaks and the other one to the positive peaks of the data resulting in an Frequency Shift Keying (FSK) signal. The results have been verified experimentally.
文摘In order to improve the data throughput of the advanced encryption standard （AES） IP core while reducing the hardware resource consumption and finally achieving a tradeoff between speed and area, a mixed pipeline architecture and reconfigurable technology for the design and implementation of the AES IP core is proposed. The encryption and decryption processes of the AES algorithm are achieved in the same process within the mixed pipeline structure. According to the finite field characterizations, the Sbox in the AES algorithm is optimized. ShiftRow and MixColumn, which are the main components in AES round transformation, are optimized with the reconfigurable technology. The design is implemented on the Xilinx Virtex2p xc2vp20-7 field programmable gate array （FPGA） device. It can achieve a data throughput above 2.58 Gbit/s, and it only requires 3 233 slices. Compared with other related designs of AES IP cores on the same device, the proposed design can achieve a tradeoff between speed and area, and obtain satisfactory results in both data throughput and hardware resource consumption.
